On Sun, Sep 27, 2026 at 04:25:31PM +0800, Max Chou wrote:
> From: Frank Chang <[email protected]>
>
> Add SiFive custom int8 matmul extension implied rules to enable the
> implied extensions of SiFive custom int8 matmul extension recursively.
>
> Signed-off-by: Frank Chang <[email protected]>
> Reviewed-by: Daniel Henrique Barboza <[email protected]>
> Reviewed-by: Alistair Francis <[email protected]>
> Signed-off-by: Max Chou <[email protected]>
Reviewed-by: Chao Liu <[email protected]>
Thanks,
Chao
> ---
> target/riscv/cpu.c | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 90fa1d714c7..714697c66cf 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2906,6 +2906,24 @@ static RISCVCPUImpliedExtsRule ZVFBFA_IMPLIED = {
> },
> };
>
> +static RISCVCPUImpliedExtsRule XSFVQMACCDOD_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_xsfvqmaccdod),
> + .implied_multi_exts = {
> + CPU_CFG_OFFSET(ext_zve32x),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule XSFVQMACCQOQ_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_xsfvqmaccqoq),
> + .implied_multi_exts = {
> + CPU_CFG_OFFSET(ext_zve32x),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] = {
> &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED,
> &RVM_IMPLIED, &RVV_IMPLIED, &RVG_IMPLIED,
> @@ -2957,6 +2975,8 @@ RISCVCPUImpliedExtsRule
> *riscv_multi_ext_implied_rules[] = {
> &SMCTR_IMPLIED,
> &SSCTR_IMPLIED,
> &SSSTATEEN_IMPLIED,
> + &XSFVQMACCDOD_IMPLIED,
> + &XSFVQMACCQOQ_IMPLIED,
> NULL
> };
>
> --
> 2.43.0
>
