On Wed, 2026-09-09 at 11:48 -0300, Daniel Henrique Barboza wrote:
> From: Chao Liu <[email protected]>
>
> RISC-V Debug Specification:
> https://github.com/riscv/riscv-debug-spec/releases/tag/1.0
>
> Add helpers to enter/leave Debug Mode and to update dpc/dcsr.
> Model resume without a Debug Module by leaving Debug Mode at
> cpu_exec_enter and continuing from dpc.
>
> Signed-off-by: Chao Liu <[email protected]>
> Reviewed-by: Daniel Henrique Barboza
> <[email protected]>
> Tested-by: Tao Tang <[email protected]>
> Signed-off-by: Daniel Henrique Barboza
> <[email protected]>
> ---
> target/riscv/cpu.h | 3 ++
> target/riscv/tcg/cpu_helper.c | 85
> +++++++++++++++++++++++++++++++++++
> target/riscv/tcg/debug.c | 5 +++
> target/riscv/tcg/tcg-cpu.c | 14 ++++++
> 4 files changed, 107 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 7b343d7a3e..82eb61a18c 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -671,6 +671,9 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr
> address, int size,
> char *riscv_isa_string(RISCVCPU *cpu);
> int riscv_cpu_max_xlen(RISCVCPUClass *mcc);
> bool riscv_cpu_option_set(RISCVCPU *cpu, const char *optname);
> +void riscv_cpu_enter_debug_mode(CPURISCVState *env, target_ulong pc,
> + uint32_t cause);
> +void riscv_cpu_leave_debug_mode(CPURISCVState *env);
>
> #ifndef CONFIG_USER_ONLY
> void riscv_cpu_do_interrupt(CPUState *cpu);
> diff --git a/target/riscv/tcg/cpu_helper.c
> b/target/riscv/tcg/cpu_helper.c
> index 07d9222652..e6d948991c 100644
> --- a/target/riscv/tcg/cpu_helper.c
> +++ b/target/riscv/tcg/cpu_helper.c
> @@ -132,6 +132,91 @@ bool
> riscv_env_smode_dbltrp_enabled(CPURISCVState *env, bool virt)
> #endif
> }
>
> +#ifndef CONFIG_USER_ONLY
> +static bool riscv_sdext_enabled(CPURISCVState *env)
> +{
> + return riscv_cpu_cfg(env)->ext_sdext;
> +}
> +#endif
> +
> +void riscv_cpu_enter_debug_mode(CPURISCVState *env, target_ulong pc,
> + uint32_t cause)
> +{
> +#ifndef CONFIG_USER_ONLY
> + if (!riscv_sdext_enabled(env)) {
> + return;
> + }
> +
> + env->debug_mode = true;
> + env->dpc = pc & get_xepc_mask(env);
> + env->dcsr &= ~(DCSR_CAUSE_MASK | DCSR_PRV_MASK | DCSR_V);
> + env->dcsr |= ((target_ulong)(cause & 0x7)) << DCSR_CAUSE_SHIFT;
You shouldn't need the cast, as DCSR is only 32-bit
> + env->dcsr |= env->priv & DCSR_PRV_MASK;
> + if (env->virt_enabled && riscv_has_ext(env, RVH)) {
> + env->dcsr |= DCSR_V;
> + }
> +
> + if (env_archcpu(env)->cfg.ext_zicfilp) {
> + if (env->elp) {
> + env->dcsr |= DCSR_PELP;
> + } else {
> + env->dcsr &= ~DCSR_PELP;
> + }
> + env->elp = false;
> + }
> +#endif
> +}
> +
> +void riscv_cpu_leave_debug_mode(CPURISCVState *env)
> +{
> +#ifndef CONFIG_USER_ONLY
> + if (!riscv_sdext_enabled(env)) {
> + return;
> + }
> +
> + target_ulong new_priv = env->dcsr & DCSR_PRV_MASK;
> + bool new_virt = riscv_has_ext(env, RVH) && (env->dcsr & DCSR_V);
These should be at the top of the function
Alistair
> +
> + if (new_priv > PRV_M) {
> + new_priv = PRV_M;
> + }
> + if (new_priv == PRV_M) {
> + new_virt = false;
> + }
> +
> + if (new_priv == PRV_S && !riscv_has_ext(env, RVS)) {
> + new_priv = PRV_M;
> + new_virt = false;
> + } else if (new_priv == PRV_U && !riscv_has_ext(env, RVU)) {
> + new_priv = riscv_has_ext(env, RVS) ? PRV_S : PRV_M;
> + new_virt = false;
> + }
> +
> + env->debug_mode = false;
> + riscv_cpu_set_mode(env, new_priv, new_virt);
> +
> + if (env_archcpu(env)->cfg.ext_zicfilp) {
> + env->elp = cpu_get_fcfien(env) && (env->dcsr & DCSR_PELP);
> + env->dcsr &= ~DCSR_PELP;
> + }
> +
> + if (new_priv != PRV_M) {
> + env->mstatus = set_field(env->mstatus, MSTATUS_MPRV, 0);
> + }
> +
> + if (env_archcpu(env)->cfg.ext_smdbltrp && new_priv != PRV_M) {
> + env->mstatus = set_field(env->mstatus, MSTATUS_MDT, 0);
> + }
> + if (env_archcpu(env)->cfg.ext_ssdbltrp && (new_priv == PRV_U ||
> new_virt)) {
> + env->mstatus = set_field(env->mstatus, MSTATUS_SDT, 0);
> + if (new_virt && new_priv == PRV_U) {
> + env->vsstatus = set_field(env->vsstatus, MSTATUS_SDT,
> 0);
> + }
> + }
> +#endif
> +}
> +
> +
> /*
> * Returns the effective PMM field.
> *
> diff --git a/target/riscv/tcg/debug.c b/target/riscv/tcg/debug.c
> index e4d719a1da..2537515f54 100644
> --- a/target/riscv/tcg/debug.c
> +++ b/target/riscv/tcg/debug.c
> @@ -973,6 +973,11 @@ void riscv_cpu_debug_excp_handler(CPUState *cs)
> RISCVCPU *cpu = RISCV_CPU(cs);
> CPURISCVState *env = &cpu->env;
>
> + /* Triggers must not match or fire while in Debug Mode. */
> + if (env->debug_mode) {
> + return;
> + }
> +
> if (cs->watchpoint_hit) {
> if (cs->watchpoint_hit->flags & BP_CPU) {
> do_trigger_action(env, DBG_ACTION_BP);
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index b68160af83..959a1e89c8 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -269,6 +269,19 @@ static vaddr riscv_pointer_wrap(CPUState *cs,
> int mmu_idx,
> }
> return extract64(result, 0, 64 - pm_len);
> }
> +
> +static void riscv_cpu_exec_enter(CPUState *cs)
> +{
> + RISCVCPU *cpu = RISCV_CPU(cs);
> + CPURISCVState *env = &cpu->env;
> +
> + if (!cpu->cfg.ext_sdext || !env->debug_mode) {
> + return;
> + }
> + target_ulong pc = env->dpc;
> + riscv_cpu_leave_debug_mode(env);
> + env->pc = pc;
> +}
> #endif
>
> const TCGCPUOps riscv_tcg_ops = {
> @@ -285,6 +298,7 @@ const TCGCPUOps riscv_tcg_ops = {
> #ifndef CONFIG_USER_ONLY
> .tlb_fill = riscv_cpu_tlb_fill,
> .pointer_wrap = riscv_pointer_wrap,
> + .cpu_exec_enter = riscv_cpu_exec_enter,
> .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
> .cpu_exec_halt = riscv_cpu_has_work,
> .cpu_exec_reset = cpu_reset,
