On Wed, 2026-09-09 at 11:48 -0300, Daniel Henrique Barboza wrote: > Adding proper TCG automated tests to sdext CSRs requires enabling > gdbstub support for riscv64, which we don't have, since the nature of > the CSRs added is that they run in a higher privilege than M mode. > > DCSR has bits to allow for context switching from other modes to > Debug > mode, but those bits must be set via an external entity (e.g. gdb) > beforehand. > > What we can do for now is a "negative" TCG test to ensure that we'll > throw illegal insn traps when trying to write sdext CSRs in machine > mode. > > Signed-off-by: Daniel Henrique Barboza > <[email protected]>
Acked-by: Alistair Francis <[email protected]> Alistair > --- > tests/tcg/riscv64/system/meson.build | 8 +++ > tests/tcg/riscv64/test-sdext-sigill.S | 83 > +++++++++++++++++++++++++++ > 2 files changed, 91 insertions(+) > create mode 100644 tests/tcg/riscv64/test-sdext-sigill.S > > diff --git a/tests/tcg/riscv64/system/meson.build > b/tests/tcg/riscv64/system/meson.build > index 8604c2a45a..6a836994e6 100644 > --- a/tests/tcg/riscv64/system/meson.build > +++ b/tests/tcg/riscv64/system/meson.build > @@ -61,6 +61,14 @@ tests += { > } > } > > +tests += { > + 'test-sdext-sigill.S': { > + 'exe_name': 'test-sdext-sigill', > + 'cflags': cflags + ['-march=rv64gcv'], > + 'qemu_args': ['-cpu', 'rv64,sdtrig=true,sdext=true', qemu_args], > + } > +} > + > if 'qemu-system-riscv64' in emulators > tcg_tests += { > 'riscv64-softmmu': { > diff --git a/tests/tcg/riscv64/test-sdext-sigill.S > b/tests/tcg/riscv64/test-sdext-sigill.S > new file mode 100644 > index 0000000000..80a6c06465 > --- /dev/null > +++ b/tests/tcg/riscv64/test-sdext-sigill.S > @@ -0,0 +1,83 @@ > +/* > + * RISC-V sdext extension "SIGILL" test: check if sdext CSRs > + * and 'dret' will throw SIGILLs outside of Debug Mode. > + * > + * Copyright (c) Qualcomm Technologies, Inc. and/or its > subsidiaries. > + * SPDX-License-Identifier: GPL-2.0-or-later > + */ > + > +.equ CSR_DCSR, 0x7b0 > +.equ CSR_DPC, 0x7b1 > +.equ CSR_DSCRATCH0, 0x7b2 > + > + .option norvc > + .text > + > + .global _start > + > +_start: > + la t0, trap_handler > + csrw mtvec, t0 > + > + dret > + j _fail > + > + li t0, 1 > + csrw CSR_DPC, t0 > + j _fail > + > + li t0, 1 > + csrw CSR_DSCRATCH0, t0 > + j _fail > + > + li t0, 1 > + csrw CSR_DCSR, t0 > + j _fail > + > + li a0, 0 > + j _exit > + > +_fail: > + li a0, 1 > + > +/* Exit through the semihosting SYS_EXIT_EXTENDED call with a0 as > the code. */ > +_exit: > + la a1, semiargs > + li t0, 0x20026 /* ADP_Stopped_ApplicationExit */ > + sd t0, 0(a1) > + sd a0, 8(a1) > + li a0, 0x20 /* TARGET_SYS_EXIT_EXTENDED */ > + .balign 16 > + slli zero, zero, 0x1f > + ebreak > + srai zero, zero, 0x7 > + j . > + > + > + .balign 4 > +trap_handler: > + csrr t4, mcause > + la t5, trap_mcause > + sd t4, 0(t5) > + csrr t4, mtval > + la t5, trap_mtval > + sd t4, 0(t5) > + csrr t4, mepc > + > + /* > + * Skip 2 insns (8 increment in mepc) to skip both the > + * insn that caused the trap and the "j _fail" insn > + * that follows it. > + */ > + addi t4, t4, 8 > + csrw mepc, t4 > + mret > + > + .data > + .balign 8 > +semiargs: > + .space 16 > +trap_mcause: > + .space 8 > +trap_mtval: > + .space 8
