As part of making virtual PCIe topology having the same apparent bandwidth as a the underlying hardware, make the generic PCIe root port support maximum speed so by default it doesn't appear to be a bottleneck.
This also makes the three generic PCIe ports (root, upstream, and downstream) have the same link speed/width capabilities. Signed-off-by: David Vrabel <[email protected]> --- hw/core/machine.c | 1 + hw/pci-bridge/gen_pcie_root_port.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/core/machine.c b/hw/core/machine.c index 8939ae1666..c4ced7a8c1 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -43,6 +43,7 @@ GlobalProperty hw_compat_11_1[] = { { "sysbus-ehci-usb", "x-migrate-fetch-addr-64bit", "off" }, { "pci-ehci-usb", "x-migrate-fetch-addr-64bit", "off" }, + { "pcie-root-port", "speed", "16" }, }; const size_t hw_compat_11_1_len = G_N_ELEMENTS(hw_compat_11_1); diff --git a/hw/pci-bridge/gen_pcie_root_port.c b/hw/pci-bridge/gen_pcie_root_port.c index d3ace7f0db..8cabeadac8 100644 --- a/hw/pci-bridge/gen_pcie_root_port.c +++ b/hw/pci-bridge/gen_pcie_root_port.c @@ -130,7 +130,7 @@ static const Property gen_rp_props[] = { DEFINE_PROP_SIZE("pref64-reserve", GenPCIERootPort, res_reserve.mem_pref_64, -1), DEFINE_PROP_PCIE_LINK_SPEED("speed", PCIESlot, - speed, PCIE_LINK_SPEED_16), + speed, PCIE_LINK_SPEED_64), DEFINE_PROP_PCIE_LINK_WIDTH("width", PCIESlot, width, PCIE_LINK_WIDTH_32), }; -- 2.43.0
