On Fri, 4 Sept 2026 at 05:37, Mohamed Mediouni <[email protected]> wrote:
>
> For the kernel-irqchip=on case, advertise ID_AA64PFR0_EL1.GIC.
>
> Signed-off-by: Mohamed Mediouni <[email protected]>
> ---
> target/arm/hvf/hvf.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
> index da3ec521fc..f881d6cc67 100644
> --- a/target/arm/hvf/hvf.c
> +++ b/target/arm/hvf/hvf.c
> @@ -1229,6 +1229,18 @@ static bool
> hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
> FIELD_DP64_IDREG(&host_isar, ID_AA64PFR1, SME, 0);
> }
>
> + /*
> + * On HVF, kernel-irqchip implies GICv3.
> + * The kernel-irqchip=off,gic-version=3 legacy case also supports
> + * the host CPU interface but advertising it in ID_AA64PFR0_EL1
> + * is not implemented yet.
> + */
> +
> + if (hvf_irqchip_in_kernel()) {
> + /* Advertise the GIC system register interface */
> + FIELD_DP64_IDREG(&host_isar, ID_AA64PFR0, GIC, 1);
> + }
How does this interact with the existing code in
hvf_arch_init_vcpu() that does:
pfr = GET_IDREG(&arm_cpu->isar, ID_AA64PFR0);
pfr |= env->gicv3state ? (1 << 24) : 0;
ret = hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64PFR0_EL1, pfr);
?
env->gicv3state should be non-NULL for both HVF and TCG
GICv3, I think, so aren't we already advertising the GIC
in ID_AA64PFR0 ?
thanks
-- PMM
