Hi Blue, and other maintainers, On Sat, Jul 28, 2012 at 8:13 PM, Blue Swirl <blauwir...@gmail.com> wrote: > On Fri, Jul 20, 2012 at 7:50 AM, Jia Liu <pro...@gmail.com> wrote: >> This is the OpenCores OpenRISC 1200 support for QEMU. >> Full implementation of the system-model and linux-user-model support. >> >> OpenRISC 1200 is a OpenCores open source CPU, >> its architecture manual can be found at >> http://opencores.org/svnget,or1k?file=/trunk/docs/openrisc_arch.pdf >> >> A OpenRISC Linux kernel contain initramfs for qemu-system-or32 testing >> can be found at >> https://docs.google.com/file/d/0BxeTrz3x0CBLSjR3Sk5Vd3h1eDA/edit?pli=1 >> >> A OpenRISC hello-world program for qemu-or32 testing can be found at >> https://docs.google.com/file/d/0BxeTrz3x0CBLN3RSWUFNYktrU2M/edit?pli=1 >> >> Signed-off-by: Jia Liu <pro...@gmail.com> > > Thanks, applied all. >
Thank you very much! Thank you all for giving me so much comment what make me know qemu better. >> --- >> >> Version History: >> >> v10: >> Addressed Peter's review comments: >> - replace field() with extract32() using for decode >> >> Addressed Max's review comments: >> - reimplement l.ff1 and l.fl1 by using ctz32() and clz32() >> - make helper func mul32 a pure 32bits mul implementation >> - add a testcase for l.mul* overflow check >> >> Addressed Max&Blue's review comments: >> - enforced instructions can be only accessible in supervisor mode >> - add exception check in softmmu mode if the CPU is not in supervisor mode >> >> v9: >> Addressed Blue's review comments: >> - fix jump instructions >> - fix some instruction decoding >> >> Addressed Andreas&Paolo's review comments: >> - rename intrpt*.c to interrupt*.c >> - use one-space indentation in Copyright Notice >> - remove unused header in cpu.c >> - remove/comment unimplement or64 code >> - remove unused macro >> - move feature into OpenRISCCPU from CPUOpenRISCState >> - move tcg_inited into initfn >> - remove reset in openrisc_*_initfn >> >> -combine target-machine into target-stubs >> >> v8: >> Addressed Max's review comments: >> - fix l.div*. >> >> Addressed Blue's review comments: >> - using qemu_log instead of printf. >> >> Addressed Peter's review comments: >> - fix load_kernel. >> >> Addressed Peter&Andreas's review comments: >> - thanks Andreas's r178 example, switch to QOM from CPUArchState. >> >> v7: >> Addressed Max's review comments: >> - fix l.div*. >> - add a div testcase. >> - add return -1 to every failed test. >> >> Addressed Peter's review comments: >> - fix load_kernel(). >> >> Addressed WeiRen's review comments: >> - fix typo, l.div and load_kernel(). >> >> v6: >> Addressed Blue's review comments: >> - reimplement l.mul* l.mfspr. >> - fix l.mtspr l.sub. >> - some English typo fix. >> - some coding style fix. >> >> Addressed Max's review comments: >> - replace NE2000 with OpenCores 10/100 ethernet adapter, thanks for his >> patch. >> >> v5: >> Addressed Blue's review comments: >> - reimplement l.mul* l.mtspr l.add* l.sub* and more. >> - shoot bugs with "--enable-debug-tcg". >> >> v4: >> Addressed Max's review comments: >> - fix l.div l.mac* l.mul*, and more. >> >> Addressed Richard, Wei-Ren and Andreas's review comments: >> - replace tcg_temp_new_i32 with tcg_temp_local_new_i32 in l.div translation. >> >> Addressed Andreas's review comments: >> - update to suit Makefile system. >> >> - add UPR CPUCFGR and MMUCFGR impelement. >> - add instruction check functions. >> >> v3: >> Addressed Stefan and Andreas's review comments: >> - use QEMU and OpenRISC's official name. >> >> Addressed Andreas's review comments: >> - reimplement cpu QOM. >> - combine target stubs and QOM implement. >> - use new commit message and subject. >> >> Addressed Max's review comments: >> - handle div zero exception. >> - reimplement float point instructions. >> - fix l.mac*, l.mul*, and more. >> >> v2: >> Addressed Malc, Weiren, Andreas and Blue's review comments: >> - reimplement cpu QOM. >> >> Addressed Andreas's review comments: >> - reimplement machine. >> - rewrite the Copyright Notice using better format. >> >> Addressed Blue and Weiren's review comments: >> - compiling with AREG0 and remove global env, no dyngen-exe longer. >> >> Addressed Max, Blue and Weiren's review comments: >> - handle div zero exception. >> - handle illegal instruction. >> >> Addressed Blue's review comments: >> - separate do_interrupt into intrpt.c form intrpt_helper.c. >> - add QEMU_NORETURN to raise_exception. >> - reimplement float instrutions. >> - fix type of linux syscall and termbits. >> - reimplement sim board. >> - use the LGPL web URL in Copyright Notice. >> - reimplemt branch instructions. >> >> - split taregt stubs, QOM and machine. >> >> v1: >> - add QEMU OpenRISC support. >> - well tested on x64 machine, and final tested x86 machine. >> >> Jia Liu (15): >> target-or32: Add target stubs and QOM cpu >> target-or32: Add MMU support >> target-or32: Add interrupt support >> target-or32: Add exception support >> target-or32: Add int instruction helpers >> target-or32: Add float instruction helpers >> target-or32: Add instruction translation >> target-or32: Add PIC support >> target-or32: Add timer support >> target-or32: Add a IIS dummy board >> target-or32: Add system instructions >> target-or32: Add gdb stub support >> target-or32: Add linux syscall, signal and termbits >> target-or32: Add linux user support >> target-or32: Add testcses >> >> arch_init.c | 2 + >> arch_init.h | 1 + >> configure | 15 +- >> cpu-exec.c | 19 + >> default-configs/or32-linux-user.mak | 1 + >> default-configs/or32-softmmu.mak | 4 + >> elf.h | 2 + >> gdbstub.c | 64 ++ >> hw/openrisc/Makefile.objs | 3 + >> hw/openrisc_pic.c | 60 ++ >> hw/openrisc_sim.c | 150 +++ >> hw/openrisc_timer.c | 101 ++ >> linux-user/elfload.c | 41 + >> linux-user/main.c | 100 ++ >> linux-user/openrisc/syscall.h | 24 + >> linux-user/openrisc/syscall_nr.h | 506 ++++++++++ >> linux-user/openrisc/target_signal.h | 26 + >> linux-user/openrisc/termbits.h | 294 ++++++ >> linux-user/signal.c | 229 +++++ >> linux-user/syscall.c | 2 +- >> linux-user/syscall_defs.h | 40 +- >> poison.h | 1 + >> target-openrisc/Makefile.objs | 4 + >> target-openrisc/cpu.c | 220 +++++ >> target-openrisc/cpu.h | 458 +++++++++ >> target-openrisc/exception.c | 27 + >> target-openrisc/exception.h | 28 + >> target-openrisc/exception_helper.c | 29 + >> target-openrisc/fpu_helper.c | 300 ++++++ >> target-openrisc/helper.h | 70 ++ >> target-openrisc/int_helper.c | 79 ++ >> target-openrisc/interrupt.c | 74 ++ >> target-openrisc/interrupt_helper.c | 57 ++ >> target-openrisc/machine.c | 47 + >> target-openrisc/mmu.c | 243 +++++ >> target-openrisc/mmu_helper.c | 63 ++ >> target-openrisc/sys_helper.c | 287 ++++++ >> target-openrisc/translate.c | 1835 >> +++++++++++++++++++++++++++++++++++ >> tests/tcg/openrisc/Makefile | 71 ++ >> tests/tcg/openrisc/test_add.c | 43 + >> tests/tcg/openrisc/test_addc.c | 38 + >> tests/tcg/openrisc/test_addi.c | 33 + >> tests/tcg/openrisc/test_addic.c | 33 + >> tests/tcg/openrisc/test_and_or.c | 65 ++ >> tests/tcg/openrisc/test_bf.c | 47 + >> tests/tcg/openrisc/test_bnf.c | 51 + >> tests/tcg/openrisc/test_div.c | 54 ++ >> tests/tcg/openrisc/test_divu.c | 34 + >> tests/tcg/openrisc/test_extx.c | 78 ++ >> tests/tcg/openrisc/test_fx.c | 57 ++ >> tests/tcg/openrisc/test_j.c | 26 + >> tests/tcg/openrisc/test_jal.c | 26 + >> tests/tcg/openrisc/test_lf_add.c | 39 + >> tests/tcg/openrisc/test_lf_div.c | 37 + >> tests/tcg/openrisc/test_lf_eqs.c | 88 ++ >> tests/tcg/openrisc/test_lf_ges.c | 88 ++ >> tests/tcg/openrisc/test_lf_gts.c | 86 ++ >> tests/tcg/openrisc/test_lf_les.c | 88 ++ >> tests/tcg/openrisc/test_lf_lts.c | 92 ++ >> tests/tcg/openrisc/test_lf_mul.c | 22 + >> tests/tcg/openrisc/test_lf_nes.c | 89 ++ >> tests/tcg/openrisc/test_lf_rem.c | 32 + >> tests/tcg/openrisc/test_lf_sub.c | 35 + >> tests/tcg/openrisc/test_logic.c | 105 ++ >> tests/tcg/openrisc/test_lx.c | 84 ++ >> tests/tcg/openrisc/test_movhi.c | 31 + >> tests/tcg/openrisc/test_mul.c | 61 ++ >> tests/tcg/openrisc/test_muli.c | 48 + >> tests/tcg/openrisc/test_mulu.c | 48 + >> tests/tcg/openrisc/test_sfeq.c | 43 + >> tests/tcg/openrisc/test_sfeqi.c | 39 + >> tests/tcg/openrisc/test_sfges.c | 44 + >> tests/tcg/openrisc/test_sfgesi.c | 40 + >> tests/tcg/openrisc/test_sfgeu.c | 44 + >> tests/tcg/openrisc/test_sfgeui.c | 41 + >> tests/tcg/openrisc/test_sfgts.c | 45 + >> tests/tcg/openrisc/test_sfgtsi.c | 41 + >> tests/tcg/openrisc/test_sfgtu.c | 43 + >> tests/tcg/openrisc/test_sfgtui.c | 42 + >> tests/tcg/openrisc/test_sfles.c | 26 + >> tests/tcg/openrisc/test_sflesi.c | 39 + >> tests/tcg/openrisc/test_sfleu.c | 43 + >> tests/tcg/openrisc/test_sfleui.c | 39 + >> tests/tcg/openrisc/test_sflts.c | 43 + >> tests/tcg/openrisc/test_sfltsi.c | 39 + >> tests/tcg/openrisc/test_sfltu.c | 43 + >> tests/tcg/openrisc/test_sfltui.c | 39 + >> tests/tcg/openrisc/test_sfne.c | 43 + >> tests/tcg/openrisc/test_sfnei.c | 39 + >> tests/tcg/openrisc/test_sub.c | 35 + >> 90 files changed, 8079 insertions(+), 6 deletions(-) >> create mode 100644 default-configs/or32-linux-user.mak >> create mode 100644 default-configs/or32-softmmu.mak >> create mode 100644 hw/openrisc/Makefile.objs >> create mode 100644 hw/openrisc_pic.c >> create mode 100644 hw/openrisc_sim.c >> create mode 100644 hw/openrisc_timer.c >> create mode 100644 linux-user/openrisc/syscall.h >> create mode 100644 linux-user/openrisc/syscall_nr.h >> create mode 100644 linux-user/openrisc/target_signal.h >> create mode 100644 linux-user/openrisc/termbits.h >> create mode 100644 target-openrisc/Makefile.objs >> create mode 100644 target-openrisc/cpu.c >> create mode 100644 target-openrisc/cpu.h >> create mode 100644 target-openrisc/exception.c >> create mode 100644 target-openrisc/exception.h >> create mode 100644 target-openrisc/exception_helper.c >> create mode 100644 target-openrisc/fpu_helper.c >> create mode 100644 target-openrisc/helper.h >> create mode 100644 target-openrisc/int_helper.c >> create mode 100644 target-openrisc/interrupt.c >> create mode 100644 target-openrisc/interrupt_helper.c >> create mode 100644 target-openrisc/machine.c >> create mode 100644 target-openrisc/mmu.c >> create mode 100644 target-openrisc/mmu_helper.c >> create mode 100644 target-openrisc/sys_helper.c >> create mode 100644 target-openrisc/translate.c >> create mode 100644 tests/tcg/openrisc/Makefile >> create mode 100644 tests/tcg/openrisc/test_add.c >> create mode 100644 tests/tcg/openrisc/test_addc.c >> create mode 100644 tests/tcg/openrisc/test_addi.c >> create mode 100644 tests/tcg/openrisc/test_addic.c >> create mode 100644 tests/tcg/openrisc/test_and_or.c >> create mode 100644 tests/tcg/openrisc/test_bf.c >> create mode 100644 tests/tcg/openrisc/test_bnf.c >> create mode 100644 tests/tcg/openrisc/test_div.c >> create mode 100644 tests/tcg/openrisc/test_divu.c >> create mode 100644 tests/tcg/openrisc/test_extx.c >> create mode 100644 tests/tcg/openrisc/test_fx.c >> create mode 100644 tests/tcg/openrisc/test_j.c >> create mode 100644 tests/tcg/openrisc/test_jal.c >> create mode 100644 tests/tcg/openrisc/test_lf_add.c >> create mode 100644 tests/tcg/openrisc/test_lf_div.c >> create mode 100644 tests/tcg/openrisc/test_lf_eqs.c >> create mode 100644 tests/tcg/openrisc/test_lf_ges.c >> create mode 100644 tests/tcg/openrisc/test_lf_gts.c >> create mode 100644 tests/tcg/openrisc/test_lf_les.c >> create mode 100644 tests/tcg/openrisc/test_lf_lts.c >> create mode 100644 tests/tcg/openrisc/test_lf_mul.c >> create mode 100644 tests/tcg/openrisc/test_lf_nes.c >> create mode 100644 tests/tcg/openrisc/test_lf_rem.c >> create mode 100644 tests/tcg/openrisc/test_lf_sub.c >> create mode 100644 tests/tcg/openrisc/test_logic.c >> create mode 100644 tests/tcg/openrisc/test_lx.c >> create mode 100644 tests/tcg/openrisc/test_movhi.c >> create mode 100644 tests/tcg/openrisc/test_mul.c >> create mode 100644 tests/tcg/openrisc/test_muli.c >> create mode 100644 tests/tcg/openrisc/test_mulu.c >> create mode 100644 tests/tcg/openrisc/test_sfeq.c >> create mode 100644 tests/tcg/openrisc/test_sfeqi.c >> create mode 100644 tests/tcg/openrisc/test_sfges.c >> create mode 100644 tests/tcg/openrisc/test_sfgesi.c >> create mode 100644 tests/tcg/openrisc/test_sfgeu.c >> create mode 100644 tests/tcg/openrisc/test_sfgeui.c >> create mode 100644 tests/tcg/openrisc/test_sfgts.c >> create mode 100644 tests/tcg/openrisc/test_sfgtsi.c >> create mode 100644 tests/tcg/openrisc/test_sfgtu.c >> create mode 100644 tests/tcg/openrisc/test_sfgtui.c >> create mode 100644 tests/tcg/openrisc/test_sfles.c >> create mode 100644 tests/tcg/openrisc/test_sflesi.c >> create mode 100644 tests/tcg/openrisc/test_sfleu.c >> create mode 100644 tests/tcg/openrisc/test_sfleui.c >> create mode 100644 tests/tcg/openrisc/test_sflts.c >> create mode 100644 tests/tcg/openrisc/test_sfltsi.c >> create mode 100644 tests/tcg/openrisc/test_sfltu.c >> create mode 100644 tests/tcg/openrisc/test_sfltui.c >> create mode 100644 tests/tcg/openrisc/test_sfne.c >> create mode 100644 tests/tcg/openrisc/test_sfnei.c >> create mode 100644 tests/tcg/openrisc/test_sub.c >> >> -- >> 1.7.9.5 >> >> Regards, Jia