On 2026-09-29 9:40, Pierrick Bouvier wrote:
In next commit, we update references for failing tests.
One test, test_mips64r6_srav, has an output that is not reproducible
on my host. After checking, it's coming from UNPREDICTABLE case
described by mips64 reference manual.
```
Format: SRAV rd, rt, rs MIPS32
Description: GPR[rd] = GPR[rt] >> GPR[rs] (arithmetic)
The contents of the low-order 32-bit word of GPR rt are shifted right,
duplicating the sign-bit (bit 31) in the emptied
bits; the word result is sign-extended and placed in GPR rd. The
bit-shift amount is specified by the low-order 5 bits
Restrictions:
On 64-bit processors, if GPR rt does not contain a sign-extended 32-bit value
(bits 63..31 equal), then the result of the
operation is UNPREDICTABLE.
```
Current implementation takes advantage of restriction above and does not
perform sign extension on lower part.
Given this definition: srav(x,y) ((int64_t)((int32_t)(x)>>(y&0b11111)))
srav(0xaaaaaaaaaaaaaaaa, 0xffffffffffffffff) = 0xffffffffffffffff
With qemu-mips64, this instruction returns 0xffffffff55555555 instead.
While this is not wrong following the spec, it can be surprising. To
have a more predictable behavior, always perform sign extension on lower
part. This will give us the advantage of having a test output that can
be checked on any host.
Signed-off-by: Pierrick Bouvier <[email protected]>
---
target/mips/tcg/translate.c | 1 +
1 file changed, 1 insertion(+)
Or simpler:
'''
target/mips: Sign-extend the SRAV operand
SRAV operates on the low-order 32-bit word of its source and
sign-extends the shifted result. Sign-extend the source before
shifting to make results deterministic when the source register
is not already sign-extended.
'''
Fixes: 48d38ca52b6 ("Switch most MIPS logical and arithmetic
instructions to TCG")
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
