Hi,
On 4/9/26 17:57, Bin Meng wrote:
Instantiate the L2CC in the PolarFire SoC machine and connect its
WayEnable register to the L2-LIM MemoryRegion. Back the complete 2 MiB
aperture and shrink it by 128 KiB for each cache way enabled.
Keep L2 Zero at its fixed aperture because it represents a cache
allocation window rather than the remaining L2-LIM capacity.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Chao Liu <[email protected]>
---
(no changes since v1)
include/hw/misc/mchp_pfsoc_l2cc.h | 1 +
include/hw/riscv/microchip_pfsoc.h | 2 ++
hw/misc/mchp_pfsoc_l2cc.c | 51 ++++++++++++++++++++++++++++++
hw/riscv/microchip_pfsoc.c | 23 +++++++-------
hw/riscv/Kconfig | 1 +
5 files changed, 67 insertions(+), 11 deletions(-)
diff --git a/include/hw/misc/mchp_pfsoc_l2cc.h
b/include/hw/misc/mchp_pfsoc_l2cc.h
index 1b5b3888d5..3a175a6340 100644
--- a/include/hw/misc/mchp_pfsoc_l2cc.h
+++ b/include/hw/misc/mchp_pfsoc_l2cc.h
@@ -22,6 +22,7 @@ typedef struct MchpPfSoCL2ccState {
SysBusDevice parent;
uint64_t regs[MCHP_PFSOC_L2CC_REG_NUM];
RegisterInfo regs_info[MCHP_PFSOC_L2CC_REG_NUM];
+ MemoryRegion *l2lim;
} MchpPfSoCL2ccState;
#define TYPE_MCHP_PFSOC_L2CC "mchp.pfsoc.l2cc"
diff --git a/include/hw/riscv/microchip_pfsoc.h
b/include/hw/riscv/microchip_pfsoc.h
index 612fd2b69c..0aeccedf77 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -27,6 +27,7 @@
#include "hw/cpu/cluster.h"
#include "hw/dma/sifive_pdma.h"
#include "hw/misc/mchp_pfsoc_dmc.h"
+#include "hw/misc/mchp_pfsoc_l2cc.h"
#include "hw/misc/mchp_pfsoc_ioscb.h"
#include "hw/misc/mchp_pfsoc_sysreg.h"
#include "hw/net/cadence_gem.h"
@@ -43,6 +44,7 @@ typedef struct MicrochipPFSoCState {
RISCVHartArrayState e_cpus;
RISCVHartArrayState u_cpus;
DeviceState *plic;
+ MchpPfSoCL2ccState l2cc;
MchpPfSoCDdrSgmiiPhyState ddr_sgmii_phy;
MchpPfSoCDdrCfgState ddr_cfg;
MchpPfSoCIoscbState ioscb;
diff --git a/hw/misc/mchp_pfsoc_l2cc.c b/hw/misc/mchp_pfsoc_l2cc.c
index 979d904676..4b87c963fc 100644
--- a/hw/misc/mchp_pfsoc_l2cc.c
+++ b/hw/misc/mchp_pfsoc_l2cc.c
@@ -11,6 +11,9 @@
#include "qemu/osdep.h"
#include "qemu/log.h"
+#include "qemu/units.h"
+#include "qapi/error.h"
+#include "hw/core/qdev-properties.h"
#include "hw/core/register.h"
#include "hw/core/registerfields.h"
#include "hw/misc/mchp_pfsoc_l2cc.h"
@@ -39,6 +42,25 @@ REG64(L2_WAY_MASK_HART4_DCACHE, 0x868)
REG64(L2_WAY_MASK_HART4_ICACHE, 0x870)
#define L2_CONFIG_RESET 0x06091004
+#define L2_LIM_WAY_COUNT 15
+#define L2_WAY_SIZE (128 * KiB)
+
+static void mchp_pfsoc_l2cc_update_l2lim(MchpPfSoCL2ccState *s,
+ uint64_t way_enable)
+{
+ uint64_t l2lim_size;
+
+ if (way_enable >= L2_LIM_WAY_COUNT) {
+ l2lim_size = 0;
+ } else {
+ l2lim_size = (L2_LIM_WAY_COUNT - way_enable) * L2_WAY_SIZE;
+ }
+
+ memory_region_transaction_begin();
+ memory_region_set_size(s->l2lim, l2lim_size);
+ memory_region_set_enabled(s->l2lim, l2lim_size != 0);
+ memory_region_transaction_commit();
+}
static uint64_t mchp_pfsoc_l2cc_way_enable_pre_write(RegisterInfo *reg,
uint64_t value)
@@ -48,6 +70,14 @@ static uint64_t
mchp_pfsoc_l2cc_way_enable_pre_write(RegisterInfo *reg,
return MAX(current, value);
}
+static void mchp_pfsoc_l2cc_way_enable_post_write(RegisterInfo *reg,
+ uint64_t value)
+{
+ MchpPfSoCL2ccState *s = MCHP_PFSOC_L2CC(reg->opaque);
+
+ mchp_pfsoc_l2cc_update_l2lim(s, value);
+}
+
#define WAY_MASK_REGISTER(_name) \
{ \
.name = "WAY_MASK_" #_name, \
@@ -66,6 +96,7 @@ static const RegisterAccessInfo mchp_pfsoc_l2cc_regs_info[] =
{
.addr = A_L2_WAY_ENABLE,
.rsvd = ~R_L2_WAY_ENABLE_VALUE_MASK,
.pre_write = mchp_pfsoc_l2cc_way_enable_pre_write,
+ .post_write = mchp_pfsoc_l2cc_way_enable_post_write,
},
WAY_MASK_REGISTER(DMA),
WAY_MASK_REGISTER(AXI4_PORT_0),
@@ -157,11 +188,31 @@ static void mchp_pfsoc_l2cc_init(Object *obj)
sysbus_init_mmio(SYS_BUS_DEVICE(obj), ®_array->mem);
}
+static void mchp_pfsoc_l2cc_realize(DeviceState *dev, Error **errp)
+{
+ MchpPfSoCL2ccState *s = MCHP_PFSOC_L2CC(dev);
+
+ if (!s->l2lim) {
+ error_setg(errp, TYPE_MCHP_PFSOC_L2CC ": 'l2-lim' link not set");
+ return;
+ }
+
+ mchp_pfsoc_l2cc_update_l2lim(s, s->regs[R_L2_WAY_ENABLE]);
+}
+
+static const Property mchp_pfsoc_l2cc_properties[] = {
+ DEFINE_PROP_LINK("l2-lim", MchpPfSoCL2ccState, l2lim,
+ TYPE_MEMORY_REGION, MemoryRegion *),
+};
+
static void mchp_pfsoc_l2cc_class_init(ObjectClass *klass, const void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
rc->phases.hold = mchp_pfsoc_l2cc_reset_hold;
+ device_class_set_props(dc, mchp_pfsoc_l2cc_properties);
+ dc->realize = mchp_pfsoc_l2cc_realize;
}
static const TypeInfo mchp_pfsoc_l2cc_info = {
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 8106dbb3ad..114567867b 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -174,6 +174,9 @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
object_initialize_child(obj, "dma-controller", &s->dma,
TYPE_SIFIVE_PDMA);
+ object_initialize_child(obj, "l2-cache-controller", &s->l2cc,
+ TYPE_MCHP_PFSOC_L2CC);
Is this the same model used by hw/riscv/sifive_u.c?
object_initialize_child(obj, "sysreg", &s->sysreg,
TYPE_MCHP_PFSOC_SYSREG);
@@ -260,18 +263,9 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
iks->clint_timebase_freq, false);
- /* L2 cache controller */
- create_unimplemented_device("microchip.pfsoc.l2cc",
- memmap[MICROCHIP_PFSOC_L2CC].base, memmap[MICROCHIP_PFSOC_L2CC].size);
-
/*
- * Add L2-LIM at reset size.
- * This should be reduced in size as the L2 Cache Controller WayEnable
- * register is incremented. Unfortunately I don't see a nice (or any) way
- * to handle reducing or blocking out the L2 LIM while still allowing it
- * be re returned to all enabled after a reset. For the time being, just
- * leave it enabled all the time. This won't break anything, but will be
- * too generous to misbehaving guests.
+ * Back the complete L2-LIM aperture. The L2 cache controller resizes
+ * this MemoryRegion to 128 KiB for every way assigned to L2-LIM.
*/
memory_region_init_ram(l2lim_mem, NULL, "microchip.pfsoc.l2lim",
memmap[MICROCHIP_PFSOC_L2LIM].size, &error_fatal);
@@ -279,6 +273,13 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev,
Error **errp)
memmap[MICROCHIP_PFSOC_L2LIM].base,
l2lim_mem);
+ /* L2 cache controller */
+ object_property_set_link(OBJECT(&s->l2cc), "l2-lim",
+ OBJECT(l2lim_mem), &error_abort);
Modelling question (I have no clue with this particular SoC): does
'l2-lim' belong to the SoC layer, consumed by the L2CC or is it
internal to the L2CC and exposed to the SoC?
+ sysbus_realize(SYS_BUS_DEVICE(&s->l2cc), errp);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->l2cc), 0,
+ memmap[MICROCHIP_PFSOC_L2CC].base);
+
/*
* HSS decompresses into the L2 zero-device window and executes there.
* Model it as RAM because QEMU does not model the backing L2 cache.
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index d06ac26648..85b535c7cb 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -18,6 +18,7 @@ config MICROCHIP_PFSOC
select DEVICE_TREE
select MCHP_PFSOC_DMC
select MCHP_PFSOC_IOSCB
+ select MCHP_PFSOC_L2CC
select MCHP_PFSOC_MMUART
select MCHP_PFSOC_SYSREG
select RISCV_ACLINT
