On Fri, Sep 04, 2026 at 11:57:39PM +0800, Bin Meng wrote: > With all previous changes, the Icicle Kit model is now able to boot > HSS v2024.06 through a Buildroot 2026.05 SD image to U-Boot and Linux. > > Document the tested source versions and exact commands to build HSS > and Buildroot. Include the sparse resize and GPT relocation steps > needed to make the generated SD image usable by QEMU. > > Also describe the RAM and serial setup, boot stages, and remaining > model limitations. > > Signed-off-by: Bin Meng <[email protected]> > --- > > (no changes since v1) > > docs/system/riscv/microchip-icicle-kit.rst | 101 +++++++++++++++++++-- > 1 file changed, 95 insertions(+), 6 deletions(-) > > diff --git a/docs/system/riscv/microchip-icicle-kit.rst > b/docs/system/riscv/microchip-icicle-kit.rst > index 38352cc62b..eeb4ff938c 100644 > --- a/docs/system/riscv/microchip-icicle-kit.rst > +++ b/docs/system/riscv/microchip-icicle-kit.rst > @@ -19,12 +19,15 @@ The ``microchip-icicle-kit`` machine supports the > following devices: > * 4 U54 cores > * Core Level Interruptor (CLINT) > * Platform-Level Interrupt Controller (PLIC) > -* L2 Loosely Integrated Memory (L2-LIM) > +* Loosely Integrated Memory (L2-LIM) > +* L2 cache controller (L2CC) > * DDR memory controller > +* System controller and system services mailbox > * 5 MMUARTs > * 1 DMA controller > * 2 GEM Ethernet controllers > * 1 SDHC storage controller > +* 1 Real-Time Clock > > The machine has a fixed 2 GiB of RAM. Other memory sizes are rejected. > The machine always exposes all five harts. Other CPU counts are rejected. > @@ -101,10 +104,96 @@ CAVEATS: > Running HSS > ----------- > > -The machine ``microchip-icicle-kit`` used to run the Hart Software Services > -(HSS_), however, the HSS development progressed and the QEMU machine > -implementation lacks behind. Currently, running the HSS no longer works. > -There is missing support in the clock and memory controller devices. In > -particular, reading from the SD card does not work. > +The ``microchip-icicle-kit`` machine can boot the Hart Software Services > +(HSS_), which then loads an HSS payload containing U-Boot from an SD card. > +The following flow was tested with HSS v2024.06 and Buildroot 2026.05. > + > +Configure HSS for the ``mpfs-icicle-kit-es`` board using its default > +configuration. QEMU provides the software-visible registers and deterministic > +status consumed by the HSS v2024.06 DDR initialization and training flow; > +it does not model the electrical properties of DDR training. HSS requires > +the RISC-V bare-metal toolchain supplied by Microchip SoftConsole to be > +available in ``PATH``. Build the tested HSS version with:
What's the reason that this is using 2024.06 by the way? Why not use the most recent release of the HSS? > + > +.. code-block:: bash > + > + $ git clone https://github.com/polarfire-soc/hart-software-services.git > + $ cd hart-software-services > + $ git checkout v2024.06 > + $ make BOARD=mpfs-icicle-kit-es defconfig > + $ make -j$(nproc) BOARD=mpfs-icicle-kit-es > + > +The HSS build creates both the raw wrapper and an eNVM programming image. > QEMU > +needs the complete eNVM image, including the 256-byte boot header added by > the > +Microchip boot mode programmer. Convert the generated Intel HEX file to a raw > +binary image, for example: > + > +.. code-block:: bash > + > + $ riscv64-unknown-elf-objcopy -I ihex -O binary \ > + build/hss-envm-wrapper.mpfs-icicle-kit-es.hex build/hss.bin > + > +Do not pass ``build/hss-envm-wrapper.bin`` directly to QEMU. That file starts > +at eNVM offset 0x100 and does not contain the boot header with the image size > +and per-hart reset vectors.
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