The Armv6-M Unprivileged/Privileged Extension is optional. While the
Cortex-M0 does not implement it, the Cortex-M0+ may - and the RP2040
Cortex-M0+ configuration in particular provides this extension.
Add the cortex-m0plus CPU type, reusing the existing Cortex-M0
initialization logic. Enable ARM_FEATURE_M_UNPRIV, introduced by commit
285e929908 ("target/arm: model Cortex-M0+ privilege extension"), and set
the Cortex-M0+ MIDR used by the RP2040.
Signed-off-by: Gilles Grimaud <[email protected]>
---
The Cortex-M0+ CPU type was previously included in:
[RFC PATCH v1 2/6] target/arm: model Cortex-M0+ privilege extension
https://lore.kernel.org/qemu-devel/[email protected]/
It is now submitted separately following review feedback.
target/arm/tcg/cpu-v7m.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c
index 48b31d5eac..ac99c93ec3 100644
--- a/target/arm/tcg/cpu-v7m.c
+++ b/target/arm/tcg/cpu-v7m.c
@@ -76,6 +76,15 @@ static void cortex_m0_initfn(Object *obj)
SET_IDREG(isar, ID_ISAR6, 0x00000000);
}
+static void cortex_m0plus_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cortex_m0_initfn(obj);
+ set_feature(&cpu->env, ARM_FEATURE_M_UNPRIV);
+ cpu->midr = 0x410cc601;
+}
+
static void cortex_m3_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
@@ -325,6 +334,8 @@ static void arm_v7m_class_init(ObjectClass *oc, const void
*data)
static const ARMCPUInfo arm_v7m_cpus[] = {
{ .name = "cortex-m0", .initfn = cortex_m0_initfn,
.class_init = arm_v7m_class_init },
+ { .name = "cortex-m0plus", .initfn = cortex_m0plus_initfn,
+ .class_init = arm_v7m_class_init },
{ .name = "cortex-m3", .initfn = cortex_m3_initfn,
.class_init = arm_v7m_class_init },
{ .name = "cortex-m4", .initfn = cortex_m4_initfn,
--
2.55.0
