Missing review: 9
Since v3:
- Rebased (s390x, x86 and some ARM patches merged)
- RISC-V posted separately as [1]
- Better describe ARM PSCI power-state update issue
Since v2:
- Make all ARM halt_reason accesses atomic, including WFI/WFE helpers
and halt-exit handling, and read event_register atomically.
- Keep the RISC-V changes focused on MIP: skip empty updates, add a
shared accessor, and convert existing MIP reads to use it.
Since v1:
- Collected Richard R-b tags (sometimes commit description updated).
- Documented the BQL and synchronization requirements of has_work().
- Renamed the callbacks to poll_during_halt() and leaving_halt().
- Addressed Peter's comments by removing racy halt-work assertions,
documenting the BQL contract, and explaining why x86 #DB delivery
through do_interrupt_all() is safe without the BQL.
- Addressed Paolo's comments by making ARM PSCI state updates atomic,
kicking remote vCPUs after power-state changes, and ensuring x86
APIC polling runs before cpu_has_work() with the BQL held only
around APIC access.
- Sanitized s390_cpu_get_state() for atomic accesses without BQL.
This series was inspired by a previous thread on the list [2].
Refactor the CPU halt-to-execution transition logic in TCG as
something more explicit and composable.
Core problem: TCGCPUOps::cpu_exec_halt callback mixed concerns,
it checked for work, processed async events, and handled state
transitions all in one place.
Solution: introduces two dedicated callbacks:
* poll_during_halt(): Process target-specific async events
before checking for work. Called early in cpu_exec().
* leaving_halt(): Perform target-specific state updates
when transitioning from halt to execution.
This separation allows the generic cpu_exec() code to orchestrate
the flow cleanly (process events, check for work, transition state).
Only 2 targets need to be migrated (x86 and ARM) then we can remove
the redundant cpu_exec_halt() hook.
The changes are expected to be purely refactoring with no functional
impact.
Testing: Usual CI.
Based-on: <[email protected]>
[1]
https://lore.kernel.org/qemu-devel/[email protected]/
[2]
https://lore.kernel.org/qemu-devel/CABgObfaDAhrpnVqQaKgG6uxPQe1YDu77YOsUEx9nqrN=3m2...@mail.gmail.com/
Philippe Mathieu-Daudé (9):
accel/tcg: Refactor poll-while-halted flow in cpu_exec()
accel/tcg: Introduce poll_during_halt() and leaving_halt()
target/arm: Split leaving-halt handling from arm_cpu_exec_halt()
target/arm: Convert cpu_exec_halt() to leaving_halt()
target/i386: Split APIC polling from x86_cpu_exec_halt()
target/i386: Split leaving-halt handling from x86_cpu_exec_halt()
target/i386: Use generic halt transition handlers
accel/tcg: Remove the redundant cpu_exec_halt() hook
target/arm: Kick vCPU after updating PSCI power state
include/accel/tcg/cpu-ops.h | 36 ++++++++++++++++-------------
target/arm/internals.h | 3 ---
target/i386/tcg/helper-tcg.h | 3 ++-
target/loongarch/internals.h | 1 -
target/riscv/internals.h | 5 ----
target/s390x/s390x-internal.h | 1 -
accel/tcg/cpu-exec.c | 20 ++++++++++------
target/alpha/cpu.c | 1 -
target/arm/arm-powerctl.c | 5 ++++
target/arm/cpu.c | 20 +++++++---------
target/arm/tcg/cpu-v7m.c | 1 -
target/avr/cpu.c | 1 -
target/hexagon/cpu.c | 1 -
target/hppa/cpu.c | 1 -
target/i386/tcg/system/seg_helper.c | 17 +++++++++-----
target/i386/tcg/tcg-cpu.c | 3 ++-
target/loongarch/cpu.c | 2 +-
target/loongarch/tcg/tcg_cpu.c | 1 -
target/m68k/cpu.c | 1 -
target/microblaze/cpu.c | 1 -
target/mips/cpu.c | 1 -
target/or1k/cpu.c | 1 -
target/ppc/cpu_init.c | 1 -
target/riscv/cpu.c | 2 +-
target/riscv/tcg/tcg-cpu.c | 1 -
target/rx/cpu.c | 1 -
target/s390x/cpu-system.c | 2 +-
target/s390x/cpu.c | 1 -
target/sh4/cpu.c | 1 -
target/sparc/cpu.c | 1 -
target/tricore/cpu.c | 1 -
target/xtensa/cpu.c | 1 -
32 files changed, 64 insertions(+), 74 deletions(-)
--
2.55.0
