On 9/11/2026 9:27 AM, Marc-André Lureau wrote:
Allow to read CSRs gated by Smstateen extension when env->debugger.
Signed-off-by: Marc-André Lureau <[email protected]>
---
target/riscv/tcg/csr.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c
index bd4b6dc114bc..93a7f419f29f 100644
--- a/target/riscv/tcg/csr.c
+++ b/target/riscv/tcg/csr.c
@@ -53,7 +53,8 @@ RISCVException smstateen_acc_ok(CPURISCVState *env, int
index, uint64_t bit)
{
bool virt = env->virt_enabled;
- if (env->priv == PRV_M || !riscv_cpu_cfg(env)->ext_smstateen) {
+ if (env->debugger || env->priv == PRV_M ||
+ !riscv_cpu_cfg(env)->ext_smstateen) {
We have an going work in qemu-riscv (sdext, currently on v10) that adds
a new 'debug' mode that is higher than the machine mode (PRV_M). It
already uses env->debugger in its logic.
I believe this change is already in line with what we want there, i.e. debug
mode having at least the same accesses as PRV_M.
Reviewed-by: Daniel Henrique Barboza <[email protected]>
return RISCV_EXCP_NONE;
}
