On Mon, 2026-09-28 at 16:58 -0300, Daniel Henrique Barboza wrote: > Hi, > > In this version we have minor changes proposed during v8, in > particular > the 'dcsr' field being an uint32_t instead of a target_ulong given > that > the reg is always 32 bits. > > No other changes made. Patches based on alistair/riscv-to- > apply.next. > > Changes from v9: > - patch 1: > - change 'dcsr' field type from target_ulong to uint32_t. > - patch 2 > - remove (target_ulong) cast when evaluating env->dcsr in > riscv_cpu_enter_debug_mode(); > - move var declarations to the top of riscv_cpu_leave_debug_mode(). > - patch 3: > - move 'retpc' var declaration up in helper_dret(). > - v9 link: > https://lore.kernel.org/qemu-devel/[email protected]/ > > > Chao Liu (6): > target/riscv: add sdext debug CSRs state > target/riscv: add sdext Debug Mode helpers > target/riscv: add dret instruction > target/riscv: add sdext enter Debug Mode on ebreak > target/riscv: add sdext single-step support > target/riscv: add sdtrig trigger action=debug mode > > Daniel Henrique Barboza (1): > tests/tcg/riscv64: add sdext "not on Debug mode" sigill tests
Thanks! Applied to riscv-to-apply.next with the comments on patch 2 fixed up Alistair > > include/exec/translation-block.h | 4 +- > target/riscv/cpu.c | 7 + > target/riscv/cpu.h | 9 ++ > target/riscv/cpu_bits.h | 33 +++++ > target/riscv/cpu_cfg_fields.h.inc | 1 + > target/riscv/helper.h | 3 + > target/riscv/insn32.decode | 1 + > target/riscv/machine.c | 22 +++ > target/riscv/tcg/cpu_helper.c | 94 +++++++++++++ > target/riscv/tcg/csr.c | 126 > ++++++++++++++++++ > target/riscv/tcg/debug.c | 59 +++++++- > .../tcg/insn_trans/trans_privileged.c.inc | 24 ++++ > target/riscv/tcg/op_helper.c | 72 ++++++++++ > target/riscv/tcg/tcg-cpu.c | 19 +++ > target/riscv/tcg/translate.c | 15 ++- > tests/tcg/riscv64/system/meson.build | 8 ++ > tests/tcg/riscv64/test-sdext-sigill.S | 83 ++++++++++++ > 17 files changed, 574 insertions(+), 6 deletions(-) > create mode 100644 tests/tcg/riscv64/test-sdext-sigill.S
