On Thu, Oct 1, 2026 at 11:55 PM Anton Johansson via qemu development
<[email protected]> wrote:
>
> Moves initialization of satp and mxl fields to a class initialization
> function that checks target_riscv64().
>
> Note: I'm aware the current iteration of this patch is rather hacky, I
> don't like the introduction of runtime_misa_mxl_max, but I'm keeping
> this in to get the series out there and collect feedback.
>
> Signed-off-by: Anton Johansson <[email protected]>
> ---
> target/riscv/cpu.h | 1 +
> target/riscv/cpu.c | 90
> +++++++++++++++++++++++++++++++++++-------------------
> 2 files changed, 59 insertions(+), 32 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 3fa322a8a9..0b17fd3db1 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -590,6 +590,7 @@ typedef struct RISCVCPUDef {
> bool bare;
> #if !defined(CONFIG_USER_ONLY)
> #if defined(CONFIG_TCG)
> + bool runtime_misa_mxl_max; /* Skip max mxl base class validation */
> const RISCVCSR *custom_csrs;
> #endif
> uint8_t irq_local_guest_max;
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index cfc80aaaf1..39501c6c9f 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -3062,6 +3062,27 @@ static void riscv_cpu_common_class_init(ObjectClass
> *c, const void *data)
> device_class_set_props(dc, riscv_cpu_properties);
> }
>
> +static void riscv_cpu_max_class_init(ObjectClass *c, const void *data)
> +{
> + RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
> + bool rv64 = target_riscv64();
> + mcc->def->misa_mxl_max = (rv64) ? MXL_RV64 : MXL_RV32;
> + mcc->def->cfg.max_satp_mode = (rv64) ? VM_1_10_SV57 : VM_1_10_SV32;
> + riscv_cpu_validate_misa_mxl(mcc);
> +}
> +
> +static void riscv_cpu_bare_class_init(ObjectClass *c, const void *data)
> +{
> + RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
> + bool rv64 = target_riscv64();
> + /*
> + * Support all available satp_mode settings. By default
> + * only MBARE will be available if the user doesn't enable
> + * a mode manually (see riscv_cpu_satp_mode_finalize()).
> + */
> + mcc->def->cfg.max_satp_mode = (rv64) ? VM_1_10_SV57 : VM_1_10_SV32;
> +}
> +
> static bool profile_extends(RISCVCPUProfile *trial, RISCVCPUProfile *parent)
> {
> RISCVCPUProfile *curr;
> @@ -3113,6 +3134,9 @@ static void riscv_cpu_class_base_init(ObjectClass *c,
> const void *data)
> if (data) {
> const RISCVCPUDef *def = data;
> mcc->def->bare |= def->bare;
> +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
> + mcc->def->runtime_misa_mxl_max |= def->runtime_misa_mxl_max;
> +#endif
> if (def->profile) {
> assert(profile_extends(def->profile, mcc->def->profile));
> assert(mcc->def->bare);
> @@ -3157,9 +3181,11 @@ static void riscv_cpu_class_base_init(ObjectClass *c,
> const void *data)
> #endif
> }
>
> - if (!object_class_is_abstract(c)) {
> +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
> + if (!object_class_is_abstract(c) && !mcc->def->runtime_misa_mxl_max) {
> riscv_cpu_validate_misa_mxl(mcc);
> }
> +#endif
> }
>
> static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,
> @@ -3365,41 +3391,41 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> ),
>
> DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_VENDOR_CPU, TYPE_RISCV_CPU),
> - DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_BARE_CPU, TYPE_RISCV_CPU,
> - /*
> - * Bare CPUs do not inherit the timer and performance
> - * counters from the parent class (see riscv_cpu_init()
> - * for info on why the parent enables them).
> - *
> - * Users have to explicitly enable these counters for
> - * bare CPUs.
> - */
> - .bare = true,
>
> - /* Set to QEMU's first supported priv version */
> - .priv_spec = PRIV_VERSION_1_10_0,
> + {
> + .name = TYPE_RISCV_BARE_CPU,
> + .parent = TYPE_RISCV_CPU,
> + .abstract = true,
> + .class_data = &(const RISCVCPUDef) {
> + /* Set to QEMU's first supported priv version */
> + .priv_spec = PRIV_VERSION_1_10_0,
> + .vext_spec = RISCV_PROFILE_ATTR_UNUSED,
>
> - /*
> - * Support all available satp_mode settings. By default
> - * only MBARE will be available if the user doesn't enable
> - * a mode manually (see riscv_cpu_satp_mode_finalize()).
> - */
> -#ifdef TARGET_RISCV32
> - .cfg.max_satp_mode = VM_1_10_SV32,
> -#else
> - .cfg.max_satp_mode = VM_1_10_SV57,
> -#endif
> - ),
> + /*
> + * Bare CPUs do not inherit the timer and performance
> + * counters from the parent class (see riscv_cpu_init()
> + * for info on why the parent enables them).
> + *
> + * Users have to explicitly enable these counters for
> + * bare CPUs.
> + */
> + .bare = true,
> + },
> + .class_init = riscv_cpu_bare_class_init,
> + },
>
> - DEFINE_RISCV_CPU(TYPE_RISCV_CPU_MAX, TYPE_RISCV_DYNAMIC_CPU,
> -#if defined(TARGET_RISCV32)
> - .misa_mxl_max = MXL_RV32,
> - .cfg.max_satp_mode = VM_1_10_SV32,
> -#elif defined(TARGET_RISCV64)
> - .misa_mxl_max = MXL_RV64,
> - .cfg.max_satp_mode = VM_1_10_SV57,
> + {
> + .name = TYPE_RISCV_CPU_MAX,
> + .parent = TYPE_RISCV_DYNAMIC_CPU,
> + .class_data = &(const RISCVCPUDef) {
> + .priv_spec = RISCV_PROFILE_ATTR_UNUSED,
> + .vext_spec = RISCV_PROFILE_ATTR_UNUSED,
> +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
> + .runtime_misa_mxl_max = true,
> #endif
> - ),
> + },
> + .class_init = riscv_cpu_max_class_init,
> + },
>
> DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E, TYPE_RISCV_VENDOR_CPU,
> .misa_ext = RVI | RVM | RVA | RVC | RVU,
>
> --
> 2.52.0
>
>
This patch is how I handle these, just for reference, not a review.
--
此致
礼
罗勇刚
Yours
sincerely,
Yonggang Luo
From 9764965c0591910d03a7c5c56e666598b600cc73 Mon Sep 17 00:00:00 2001
From: Yonggang Luo <[email protected]>
Date: Fri, 11 Sep 2026 17:55:19 +0800
Subject: [PATCH 2/2] target/riscv: gate CPU types with TargetInfo
Gate CPU types with TypeInfo.is_available instead of
TARGET_RISCV32/64: DEFINE_RISCV_CPU_AVAIL, DEFINE_RISCV64_CPU, and
DEFINE_RISCV_CPU_32_64SYS.
Add RISCVCPUDef.target_init. max and bare keep RV64/SV57 in the
TypeInfo; on riscv32 the callbacks set RV32/SV32 after merge. Do
not inherit the parent pointer. Validate RV64/128 misa_mxl_max only
when not target_riscv32().
Signed-off-by: Yonggang Luo <[email protected]>
---
target/riscv/cpu.c | 131 ++++++++++++++++++++++++++++++---------------
target/riscv/cpu.h | 7 +++
2 files changed, 96 insertions(+), 42 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c6f1739075..ad161d58dc 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1586,18 +1586,37 @@ static const MISAExtInfo misa_ext_info_arr[] = {
MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)")
};
+static void riscv_max_target_init(RISCVCPUClass *mcc)
+{
+ if (!target_riscv32()) {
+ return;
+ }
+ mcc->def->misa_mxl_max = MXL_RV32;
+ mcc->def->cfg.max_satp_mode = VM_1_10_SV32;
+}
+
+static void riscv_bare_target_init(RISCVCPUClass *mcc)
+{
+ if (!target_riscv32()) {
+ return;
+ }
+ /* BARE has no misa_mxl_max, so the class_base_init satp clamp skips it. */
+ mcc->def->cfg.max_satp_mode = VM_1_10_SV32;
+}
+
static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
{
CPUClass *cc = CPU_CLASS(mcc);
/* Validate that MISA_MXL is set properly. */
switch (mcc->def->misa_mxl_max) {
-#ifdef TARGET_RISCV64
case MXL_RV64:
case MXL_RV128:
+ if (target_riscv32()) {
+ g_assert_not_reached();
+ }
cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
break;
-#endif
case MXL_RV32:
cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
break;
@@ -3092,6 +3111,8 @@ static void riscv_cpu_class_base_init(ObjectClass *c,
const void *data)
if (pcc->def) {
mcc->def = g_memdup2(pcc->def, sizeof(*pcc->def));
+ /* TypeInfo supplies target_init; do not inherit the parent pointer. */
+ mcc->def->target_init = NULL;
} else {
mcc->def = g_new0(RISCVCPUDef, 1);
}
@@ -3152,6 +3173,9 @@ static void riscv_cpu_class_base_init(ObjectClass *c,
const void *data)
mcc->def->custom_csrs = def->custom_csrs;
}
#endif
+ if (def->target_init) {
+ def->target_init(mcc);
+ }
}
if (!object_class_is_abstract(c)) {
@@ -3262,6 +3286,7 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char
*nodename)
.name = (type_name), \
.parent = (parent_type_name), \
.abstract = true, \
+ .is_available = target_is_base_riscv, \
.class_data = &(const RISCVCPUDef) { \
.priv_spec = RISCV_PROFILE_ATTR_UNUSED, \
.vext_spec = RISCV_PROFILE_ATTR_UNUSED, \
@@ -3270,10 +3295,11 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char
*nodename)
}, \
}
-#define DEFINE_RISCV_CPU(type_name, parent_type_name, ...) \
+#define DEFINE_RISCV_CPU_AVAIL(type_name, parent_type_name, avail, ...) \
{ \
.name = (type_name), \
.parent = (parent_type_name), \
+ .is_available = (avail), \
.class_data = &(const RISCVCPUDef) { \
.priv_spec = RISCV_PROFILE_ATTR_UNUSED, \
.vext_spec = RISCV_PROFILE_ATTR_UNUSED, \
@@ -3282,8 +3308,37 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char
*nodename)
}, \
}
+#define DEFINE_RISCV_CPU(type_name, parent_type_name, ...) \
+ DEFINE_RISCV_CPU_AVAIL(type_name, parent_type_name, \
+ target_is_base_riscv, __VA_ARGS__)
+
+#define DEFINE_RISCV64_CPU(type_name, parent_type_name, ...) \
+ DEFINE_RISCV_CPU_AVAIL(type_name, parent_type_name, \
+ target_is_riscv64, __VA_ARGS__)
+
+/*
+ * Original:
+ * #if defined(TARGET_RISCV32) || \
+ * (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY))
+ *
+ * RV32 models on every riscv32 binary, and on system riscv64
+ * (-cpu rv32 / e31 / ibex). Not linux-user riscv64.
+ */
+static bool riscv32_64sys_available(const TargetInfo *ti)
+{
+#ifdef CONFIG_USER_ONLY
+ return target_is_riscv32(ti);
+#else
+ return target_is_base_riscv(ti);
+#endif
+}
+
+#define DEFINE_RISCV_CPU_32_64SYS(type_name, parent_type_name, ...) \
+ DEFINE_RISCV_CPU_AVAIL(type_name, parent_type_name, \
+ riscv32_64sys_available, __VA_ARGS__)
+
#define DEFINE_PROFILE_CPU(type_name, parent_type_name, profile_) \
- DEFINE_RISCV_CPU(type_name, parent_type_name, \
+ DEFINE_RISCV64_CPU(type_name, parent_type_name, \
.profile = &(profile_))
static void riscv_cpu_instance_finalize(Object *obj)
@@ -3311,6 +3366,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.class_size = sizeof(RISCVCPUClass),
.class_init = riscv_cpu_common_class_init,
.class_base_init = riscv_cpu_class_base_init,
+ .is_available = target_is_base_riscv,
},
DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_DYNAMIC_CPU, TYPE_RISCV_CPU,
@@ -3339,21 +3395,14 @@ static const TypeInfo riscv_cpu_type_infos[] = {
* only MBARE will be available if the user doesn't enable
* a mode manually (see riscv_cpu_satp_mode_finalize()).
*/
-#ifdef TARGET_RISCV32
- .cfg.max_satp_mode = VM_1_10_SV32,
-#else
.cfg.max_satp_mode = VM_1_10_SV57,
-#endif
+ .target_init = riscv_bare_target_init,
),
DEFINE_RISCV_CPU(TYPE_RISCV_CPU_MAX, TYPE_RISCV_DYNAMIC_CPU,
-#if defined(TARGET_RISCV32)
- .misa_mxl_max = MXL_RV32,
- .cfg.max_satp_mode = VM_1_10_SV32,
-#elif defined(TARGET_RISCV64)
.misa_mxl_max = MXL_RV64,
.cfg.max_satp_mode = VM_1_10_SV57,
-#endif
+ .target_init = riscv_max_target_init,
),
DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E, TYPE_RISCV_VENDOR_CPU,
@@ -3378,9 +3427,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.cfg.pmp_regions = 8
),
-#if defined(TARGET_RISCV32) || \
- (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY))
- DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE32, TYPE_RISCV_DYNAMIC_CPU,
+ DEFINE_RISCV_CPU_32_64SYS(TYPE_RISCV_CPU_BASE32, TYPE_RISCV_DYNAMIC_CPU,
.cfg.max_satp_mode = VM_1_10_SV32,
.misa_mxl_max = MXL_RV32,
@@ -3406,7 +3453,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.cfg.ext_svvptc = true,
),
- DEFINE_RISCV_CPU(TYPE_RISCV_CPU_IBEX, TYPE_RISCV_VENDOR_CPU,
+ DEFINE_RISCV_CPU_32_64SYS(TYPE_RISCV_CPU_IBEX, TYPE_RISCV_VENDOR_CPU,
.misa_mxl_max = MXL_RV32,
.misa_ext = RVI | RVM | RVC | RVU,
.priv_spec = PRIV_VERSION_1_12_0,
@@ -3423,37 +3470,38 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.cfg.ext_xlrbr = true
),
- DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E31, TYPE_RISCV_CPU_SIFIVE_E,
+ DEFINE_RISCV_CPU_32_64SYS(TYPE_RISCV_CPU_SIFIVE_E31,
+ TYPE_RISCV_CPU_SIFIVE_E,
.misa_mxl_max = MXL_RV32
),
- DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E34, TYPE_RISCV_CPU_SIFIVE_E,
+ DEFINE_RISCV_CPU_32_64SYS(TYPE_RISCV_CPU_SIFIVE_E34,
+ TYPE_RISCV_CPU_SIFIVE_E,
.misa_mxl_max = MXL_RV32,
.misa_ext = RVF, /* IMAFCU */
),
- DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_U34, TYPE_RISCV_CPU_SIFIVE_U,
+ DEFINE_RISCV_CPU_32_64SYS(TYPE_RISCV_CPU_SIFIVE_U34,
+ TYPE_RISCV_CPU_SIFIVE_U,
.misa_mxl_max = MXL_RV32,
),
- DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV32I, TYPE_RISCV_BARE_CPU,
+ DEFINE_RISCV_CPU_32_64SYS(TYPE_RISCV_CPU_RV32I, TYPE_RISCV_BARE_CPU,
.misa_mxl_max = MXL_RV32,
.misa_ext = RVI
),
- DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV32E, TYPE_RISCV_BARE_CPU,
+ DEFINE_RISCV_CPU_32_64SYS(TYPE_RISCV_CPU_RV32E, TYPE_RISCV_BARE_CPU,
.misa_mxl_max = MXL_RV32,
.misa_ext = RVE
),
-#endif
-#if (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY))
- DEFINE_RISCV_CPU(TYPE_RISCV_CPU_MAX32, TYPE_RISCV_DYNAMIC_CPU,
+#ifndef CONFIG_USER_ONLY
+ DEFINE_RISCV64_CPU(TYPE_RISCV_CPU_MAX32, TYPE_RISCV_DYNAMIC_CPU,
.cfg.max_satp_mode = VM_1_10_SV32,
.misa_mxl_max = MXL_RV32,
),
#endif
-#if defined(TARGET_RISCV64)
- DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE64, TYPE_RISCV_DYNAMIC_CPU,
+ DEFINE_RISCV64_CPU(TYPE_RISCV_CPU_BASE64, TYPE_RISCV_DYNAMIC_CPU,
.cfg.max_satp_mode = VM_1_10_SV57,
.misa_mxl_max = MXL_RV64,
@@ -3479,19 +3527,19 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.cfg.ext_svvptc = true,
),
- DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E51, TYPE_RISCV_CPU_SIFIVE_E,
+ DEFINE_RISCV64_CPU(TYPE_RISCV_CPU_SIFIVE_E51, TYPE_RISCV_CPU_SIFIVE_E,
.misa_mxl_max = MXL_RV64
),
- DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_U54, TYPE_RISCV_CPU_SIFIVE_U,
+ DEFINE_RISCV64_CPU(TYPE_RISCV_CPU_SIFIVE_U54, TYPE_RISCV_CPU_SIFIVE_U,
.misa_mxl_max = MXL_RV64,
),
- DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SHAKTI_C, TYPE_RISCV_CPU_SIFIVE_U,
+ DEFINE_RISCV64_CPU(TYPE_RISCV_CPU_SHAKTI_C, TYPE_RISCV_CPU_SIFIVE_U,
.misa_mxl_max = MXL_RV64,
),
- DEFINE_RISCV_CPU(TYPE_RISCV_CPU_THEAD_C906, TYPE_RISCV_VENDOR_CPU,
+ DEFINE_RISCV64_CPU(TYPE_RISCV_CPU_THEAD_C906, TYPE_RISCV_VENDOR_CPU,
.misa_mxl_max = MXL_RV64,
.misa_ext = RVG | RVC | RVS | RVU,
.priv_spec = PRIV_VERSION_1_11_0,
@@ -3519,7 +3567,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
#endif
),
- DEFINE_RISCV_CPU(TYPE_RISCV_CPU_THEAD_C908, TYPE_RISCV_VENDOR_CPU,
+ DEFINE_RISCV64_CPU(TYPE_RISCV_CPU_THEAD_C908, TYPE_RISCV_VENDOR_CPU,
.misa_mxl_max = MXL_RV64,
.misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU,
.priv_spec = PRIV_VERSION_1_12_0,
@@ -3566,12 +3614,12 @@ static const TypeInfo riscv_cpu_type_infos[] = {
#endif
),
- DEFINE_RISCV_CPU(TYPE_RISCV_CPU_THEAD_C908V, TYPE_RISCV_CPU_THEAD_C908,
+ DEFINE_RISCV64_CPU(TYPE_RISCV_CPU_THEAD_C908V, TYPE_RISCV_CPU_THEAD_C908,
.misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV,
.vext_spec = VEXT_VERSION_1_00_0,
),
- DEFINE_RISCV_CPU(TYPE_RISCV_CPU_TT_ASCALON, TYPE_RISCV_VENDOR_CPU,
+ DEFINE_RISCV64_CPU(TYPE_RISCV_CPU_TT_ASCALON, TYPE_RISCV_VENDOR_CPU,
.misa_mxl_max = MXL_RV64,
.misa_ext = RVG | RVC | RVS | RVU | RVH | RVV,
.priv_spec = PRIV_VERSION_1_13_0,
@@ -3635,7 +3683,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.cfg.max_satp_mode = VM_1_10_SV57,
),
- DEFINE_RISCV_CPU(TYPE_RISCV_CPU_VEYRON_V1, TYPE_RISCV_VENDOR_CPU,
+ DEFINE_RISCV64_CPU(TYPE_RISCV_CPU_VEYRON_V1, TYPE_RISCV_VENDOR_CPU,
.misa_mxl_max = MXL_RV64,
.misa_ext = RVG | RVC | RVS | RVU | RVH,
.priv_spec = PRIV_VERSION_1_12_0,
@@ -3671,7 +3719,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.cfg.max_satp_mode = VM_1_10_SV48,
),
- DEFINE_RISCV_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU, TYPE_RISCV_VENDOR_CPU,
+ DEFINE_RISCV64_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU, TYPE_RISCV_VENDOR_CPU,
.misa_mxl_max = MXL_RV64,
.misa_ext = RVG | RVC | RVB | RVS | RVU,
.priv_spec = PRIV_VERSION_1_12_0,
@@ -3694,7 +3742,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.cfg.max_satp_mode = VM_1_10_SV39,
),
- DEFINE_RISCV_CPU(TYPE_RISCV_CPU_XIANGSHAN_KMH, TYPE_RISCV_VENDOR_CPU,
+ DEFINE_RISCV64_CPU(TYPE_RISCV_CPU_XIANGSHAN_KMH, TYPE_RISCV_VENDOR_CPU,
.misa_mxl_max = MXL_RV64,
.misa_ext = RVG | RVC | RVB | RVS | RVU | RVH | RVV,
.priv_spec = PRIV_VERSION_1_13_0,
@@ -3754,7 +3802,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
),
/* https://mips.com/products/hardware/p8700/ */
- DEFINE_RISCV_CPU(TYPE_RISCV_CPU_MIPS_P8700, TYPE_RISCV_VENDOR_CPU,
+ DEFINE_RISCV64_CPU(TYPE_RISCV_CPU_MIPS_P8700, TYPE_RISCV_VENDOR_CPU,
.misa_mxl_max = MXL_RV64,
.misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU,
.priv_spec = PRIV_VERSION_1_12_0,
@@ -3777,16 +3825,16 @@ static const TypeInfo riscv_cpu_type_infos[] = {
),
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
- DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE128, TYPE_RISCV_DYNAMIC_CPU,
+ DEFINE_RISCV64_CPU(TYPE_RISCV_CPU_BASE128, TYPE_RISCV_DYNAMIC_CPU,
.cfg.max_satp_mode = VM_1_10_SV57,
.misa_mxl_max = MXL_RV128,
),
#endif /* CONFIG_TCG */
- DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV64I, TYPE_RISCV_BARE_CPU,
+ DEFINE_RISCV64_CPU(TYPE_RISCV_CPU_RV64I, TYPE_RISCV_BARE_CPU,
.misa_mxl_max = MXL_RV64,
.misa_ext = RVI
),
- DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV64E, TYPE_RISCV_BARE_CPU,
+ DEFINE_RISCV64_CPU(TYPE_RISCV_CPU_RV64E, TYPE_RISCV_BARE_CPU,
.misa_mxl_max = MXL_RV64,
.misa_ext = RVE
),
@@ -3795,7 +3843,6 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, TYPE_RISCV_CPU_RV64I,
RVA22S64),
DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA23U64, TYPE_RISCV_CPU_RV64I,
RVA23U64),
DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA23S64, TYPE_RISCV_CPU_RV64I,
RVA23S64),
-#endif /* TARGET_RISCV64 */
};
DEFINE_TYPES(riscv_cpu_type_infos)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 034d7e96c4..265c632206 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -597,6 +597,13 @@ typedef struct RISCVCPUDef {
#endif
/* This is just a setter for env->num_triggers. */
uint32_t num_triggers;
+
+ /*
+ * Optional per-CPU callback run from riscv_cpu_class_base_init
+ * after the static def is merged. Use it to adjust fields that
+ * depend on the build target (e.g. clamp misa_mxl_max for RV32).
+ */
+ void (*target_init)(struct RISCVCPUClass *mcc);
} RISCVCPUDef;
/**
--
2.55.0.windows.3
