SRAV operates on the low-order 32-bit word of its source and
sign-extends the shifted result. Sign-extend the source before
shifting to make results deterministic when the source register
is not already sign-extended.
Fixes: 48d38ca52b6 ("Switch most MIPS logical and arithmetic instructions to
TCG")
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Acked-by: Philippe Mathieu-Daudé <[email protected]>
Tested-by: Philippe Mathieu-Daudé <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Pierrick Bouvier <[email protected]>
---
target/mips/tcg/translate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index e3467d15251..936f8c4eddc 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -2853,6 +2853,7 @@ static void gen_shift(DisasContext *ctx, uint32_t opc,
tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
break;
case OPC_SRAV:
+ tcg_gen_ext32s_tl(t1, t1);
tcg_gen_andi_tl(t0, t0, 0x1f);
tcg_gen_sar_tl(cpu_gpr[rd], t1, t0);
break;
--
2.43.0
