Writes to UCR2, USR1, and USR2 modify state that feeds into
imx_update() but did not call it to re-evaluate the IRQ line. For
instance, a guest clearing a status bit in USR1 (write-1-to-clear)
would not deassert the corresponding interrupt.
Fixes: 40b6f91151e7 ("i.MX: UART support")
Reported-by: Pavee Hui <[email protected]>
Signed-off-by: Marc-André Lureau <[email protected]>
---
hw/char/imx_serial.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
index 8ac4efbb5e98..7a3d575c964d 100644
--- a/hw/char/imx_serial.c
+++ b/hw/char/imx_serial.c
@@ -324,12 +324,14 @@ static void imx_serial_write(void *opaque, hwaddr offset,
}
}
s->ucr2 = value & 0xffff;
+ imx_update(s);
break;
case 0x25: /* USR1 */
value &= USR1_AWAKE | USR1_AIRINT | USR1_DTRD | USR1_AGTIM |
USR1_FRAMERR | USR1_ESCF | USR1_RTSD | USR1_PARTYER;
s->usr1 &= ~value;
+ imx_update(s);
break;
case 0x26: /* USR2 */
@@ -341,6 +343,7 @@ static void imx_serial_write(void *opaque, hwaddr offset,
USR2_RIDELT | USR2_IRINT | USR2_WAKE |
USR2_DCDDELT | USR2_RTSF | USR2_BRCD | USR2_ORE;
s->usr2 &= ~value;
+ imx_update(s);
break;
/*
--
2.56.0.rc0.29.g47ce80527c56
