On 10/4/2026 8:26 PM, Brian Cain wrote: > Signed-off-by: Brian Cain <[email protected]> > --- > target/hexagon/gen_tcg_hvx.h | 242 ++++++++++++------------ > target/hexagon/mmvec/macros.h | 8 +- > target/hexagon/genptr.c | 18 +- > target/hexagon/mmvec/system_ext_mmvec.c | 8 +- > target/hexagon/op_helper.c | 34 ++-- > 5 files changed, 152 insertions(+), 158 deletions(-) > > diff --git a/target/hexagon/gen_tcg_hvx.h b/target/hexagon/gen_tcg_hvx.h > index 548b49b4156..e439b0817f2 100644 > --- a/target/hexagon/gen_tcg_hvx.h > +++ b/target/hexagon/gen_tcg_hvx.h > @@ -126,19 +126,19 @@ static inline void assert_vhist_tmp(DisasContext *ctx) > > #define fGEN_TCG_V6_vassign(SHORTCODE) \ > tcg_gen_gvec_mov_var(MO_64, VdV_base, VdV_off, VuV_base, VuV_off, \ > - sizeof(MMVector), sizeof(MMVector)) > + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) > > #define fGEN_TCG_V6_vassign_tmp(SHORTCODE) \ > tcg_gen_gvec_mov_var(MO_64, VdV_base, VdV_off, VuV_base, VuV_off, \ > - sizeof(MMVector), sizeof(MMVector)) > + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) > > #define fGEN_TCG_V6_vcombine_tmp(SHORTCODE) \ > do { \ > tcg_gen_gvec_mov_var(MO_64, VddV_base, VddV_off, VvV_base, VvV_off, \ > - sizeof(MMVector), sizeof(MMVector)); \ > + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ > tcg_gen_gvec_mov_var(MO_64, VddV_base, VddV_off + sizeof(MMVector), \ > - VuV_base, VuV_off, sizeof(MMVector), \ > - sizeof(MMVector)); \ > + VuV_base, VuV_off, VECTOR_SIZE_BYTE, \ > + VECTOR_SIZE_BYTE); \ > } while (0) > > /* > @@ -150,19 +150,19 @@ static inline void assert_vhist_tmp(DisasContext *ctx) > do { \ > if (VddV_off != VuV_off) { \ > tcg_gen_gvec_mov_var(MO_64, VddV_base, VddV_off, VvV_base, \ > - VvV_off, sizeof(MMVector), > sizeof(MMVector)); \ > + VvV_off, VECTOR_SIZE_BYTE, > VECTOR_SIZE_BYTE); \ > tcg_gen_gvec_mov_var(MO_64, VddV_base, \ > VddV_off + sizeof(MMVector), VuV_base, \ > - VuV_off, sizeof(MMVector), > sizeof(MMVector)); \ > + VuV_off, VECTOR_SIZE_BYTE, > VECTOR_SIZE_BYTE); \ > } else { \ > intptr_t tmpoff = offsetof(CPUHexagonState, vtmp); \ > tcg_gen_gvec_mov_var(MO_64, tcg_env, tmpoff, VuV_base, VuV_off, \ > - sizeof(MMVector), sizeof(MMVector)); \ > + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ > tcg_gen_gvec_mov_var(MO_64, VddV_base, VddV_off, VvV_base, \ > - VvV_off, sizeof(MMVector), > sizeof(MMVector)); \ > + VvV_off, VECTOR_SIZE_BYTE, > VECTOR_SIZE_BYTE); \ > tcg_gen_gvec_mov_var(MO_64, VddV_base, \ > VddV_off + sizeof(MMVector), tcg_env, > tmpoff, \ > - sizeof(MMVector), sizeof(MMVector)); \ > + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ > } \ > } while (0) > > @@ -174,7 +174,7 @@ static inline void assert_vhist_tmp(DisasContext *ctx) > tcg_gen_andi_tl(lsb, PsV, 1); \ > tcg_gen_brcondi_tl(TCG_COND_NE, lsb, PRED, false_label); \ > tcg_gen_gvec_mov_var(MO_64, VdV_base, VdV_off, VuV_base, VuV_off, \ > - sizeof(MMVector), sizeof(MMVector)); \ > + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ > gen_set_label(false_label); \ > } while (0) > > @@ -190,62 +190,52 @@ static inline void assert_vhist_tmp(DisasContext *ctx) > /* Vector add - various forms */ > #define fGEN_TCG_V6_vaddb(SHORTCODE) \ > tcg_gen_gvec_add_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, > VvV_base, \ > - VvV_off, sizeof(MMVector), sizeof(MMVector)) > + VvV_off, VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) > > #define fGEN_TCG_V6_vaddh(SHORTCYDE) \ > tcg_gen_gvec_add_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ > - VvV_base, VvV_off, sizeof(MMVector), \ > - sizeof(MMVector)) > + VvV_base, VvV_off, VECTOR_SIZE_BYTE, \ > + VECTOR_SIZE_BYTE) > > #define fGEN_TCG_V6_vaddw(SHORTCODE) \ > tcg_gen_gvec_add_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off, \ > - VvV_base, VvV_off, sizeof(MMVector), \ > - sizeof(MMVector)) > + VvV_base, VvV_off, VECTOR_SIZE_BYTE, \ > + VECTOR_SIZE_BYTE) > > -#define fGEN_TCG_V6_vaddb_dv(SHORTCODE) \ > - tcg_gen_gvec_add_var(MO_8, VddV_base, VddV_off, VuuV_base, VuuV_off, \ > - VvvV_base, VvvV_off, sizeof(MMVector) * 2, \ > - sizeof(MMVector) * 2) > +#define fGEN_TCG_PAIR_ADDSUB_BASIC(OP, VECE) \ > + do { \ > + tcg_gen_gvec_##OP##_var(VECE, VddV_base, VddV_off, \ > + VuuV_base, VuuV_off, VvvV_base, VvvV_off, \ > + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ > + tcg_gen_gvec_##OP##_var(VECE, VddV_base, \ > + VddV_off + sizeof(MMVector), VuuV_base, \ > + VuuV_off + sizeof(MMVector), VvvV_base, \ > + VvvV_off + sizeof(MMVector), \ > + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ > + } while (0) > > -#define fGEN_TCG_V6_vaddh_dv(SHORTCYDE) \ > - tcg_gen_gvec_add_var(MO_16, VddV_base, VddV_off, VuuV_base, VuuV_off, \ > - VvvV_base, VvvV_off, sizeof(MMVector) * 2, \ > - sizeof(MMVector) * 2) > - > -#define fGEN_TCG_V6_vaddw_dv(SHORTCODE) \ > - tcg_gen_gvec_add_var(MO_32, VddV_base, VddV_off, VuuV_base, VuuV_off, \ > - VvvV_base, VvvV_off, sizeof(MMVector) * 2, \ > - sizeof(MMVector) * 2) > +#define fGEN_TCG_V6_vaddb_dv(SHORTCODE) fGEN_TCG_PAIR_ADDSUB_BASIC(add, MO_8) > +#define fGEN_TCG_V6_vaddh_dv(SHORTCYDE) fGEN_TCG_PAIR_ADDSUB_BASIC(add, > MO_16) > +#define fGEN_TCG_V6_vaddw_dv(SHORTCODE) fGEN_TCG_PAIR_ADDSUB_BASIC(add, > MO_32) > > /* Vector sub - various forms */ > #define fGEN_TCG_V6_vsubb(SHORTCODE) \ > tcg_gen_gvec_sub_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, > VvV_base, \ > - VvV_off, sizeof(MMVector), sizeof(MMVector)) > + VvV_off, VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) > > #define fGEN_TCG_V6_vsubh(SHORTCODE) \ > tcg_gen_gvec_sub_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ > - VvV_base, VvV_off, sizeof(MMVector), \ > - sizeof(MMVector)) > + VvV_base, VvV_off, VECTOR_SIZE_BYTE, \ > + VECTOR_SIZE_BYTE) > > #define fGEN_TCG_V6_vsubw(SHORTCODE) \ > tcg_gen_gvec_sub_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off, \ > - VvV_base, VvV_off, sizeof(MMVector), \ > - sizeof(MMVector)) > + VvV_base, VvV_off, VECTOR_SIZE_BYTE, \ > + VECTOR_SIZE_BYTE) > > -#define fGEN_TCG_V6_vsubb_dv(SHORTCODE) \ > - tcg_gen_gvec_sub_var(MO_8, VddV_base, VddV_off, VuuV_base, VuuV_off, \ > - VvvV_base, VvvV_off, sizeof(MMVector) * 2, \ > - sizeof(MMVector) * 2) > - > -#define fGEN_TCG_V6_vsubh_dv(SHORTCODE) \ > - tcg_gen_gvec_sub_var(MO_16, VddV_base, VddV_off, VuuV_base, VuuV_off, \ > - VvvV_base, VvvV_off, sizeof(MMVector) * 2, \ > - sizeof(MMVector) * 2) > - > -#define fGEN_TCG_V6_vsubw_dv(SHORTCODE) \ > - tcg_gen_gvec_sub_var(MO_32, VddV_base, VddV_off, VuuV_base, VuuV_off, \ > - VvvV_base, VvvV_off, sizeof(MMVector) * 2, \ > - sizeof(MMVector) * 2) > +#define fGEN_TCG_V6_vsubb_dv(SHORTCODE) fGEN_TCG_PAIR_ADDSUB_BASIC(sub, MO_8) > +#define fGEN_TCG_V6_vsubh_dv(SHORTCODE) fGEN_TCG_PAIR_ADDSUB_BASIC(sub, > MO_16) > +#define fGEN_TCG_V6_vsubw_dv(SHORTCODE) fGEN_TCG_PAIR_ADDSUB_BASIC(sub, > MO_32) > > #define fGEN_TCG_V6_vaddbsat(SHORTCODE) \ > tcg_gen_gvec_ssadd_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, \ > @@ -278,8 +268,14 @@ static inline void assert_vhist_tmp(DisasContext *ctx) > VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) > > #define fGEN_TCG_PAIR_ADDSUB(OP, VECE, DBASE, DST, ABASE, SRC_A, BBASE, > SRC_B) \ > - tcg_gen_gvec_##OP##_var(VECE, DBASE, DST, ABASE, SRC_A, BBASE, SRC_B, \ > - 2 * VECTOR_SIZE_BYTE, 2 * VECTOR_SIZE_BYTE) > + do { \ > + tcg_gen_gvec_##OP##_var(VECE, DBASE, DST, ABASE, SRC_A, BBASE, > SRC_B, \ > + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ > + tcg_gen_gvec_##OP##_var(VECE, DBASE, DST + sizeof(MMVector), \ > + ABASE, SRC_A + sizeof(MMVector), \ > + BBASE, SRC_B + sizeof(MMVector), \ > + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ > + } while (0) > > #define fGEN_TCG_V6_vaddbsat_dv(SHORTCODE) \ > fGEN_TCG_PAIR_ADDSUB(ssadd, MO_8, VddV_base, VddV_off, \ > @@ -458,7 +454,7 @@ static inline void assert_vhist_tmp(DisasContext *ctx) > TCGv shift = tcg_temp_new(); \ > tcg_gen_andi_tl(shift, RtV, 15); \ > tcg_gen_gvec_sars_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ > - shift, sizeof(MMVector), sizeof(MMVector)); \ > + shift, VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ > } while (0) > > #define fGEN_TCG_V6_vasrh_acc(SHORTCODE) \ > @@ -467,10 +463,10 @@ static inline void assert_vhist_tmp(DisasContext *ctx) > TCGv shift = tcg_temp_new(); \ > tcg_gen_andi_tl(shift, RtV, 15); \ > tcg_gen_gvec_sars_var(MO_16, tcg_env, tmpoff, VuV_base, VuV_off, \ > - shift, sizeof(MMVector), sizeof(MMVector)); \ > + shift, VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ > tcg_gen_gvec_add_var(MO_16, VxV_base, VxV_off, VxV_base, VxV_off, \ > - tcg_env, tmpoff, sizeof(MMVector), \ > - sizeof(MMVector)); \ > + tcg_env, tmpoff, VECTOR_SIZE_BYTE, \ > + VECTOR_SIZE_BYTE); \ > } while (0) > > #define fGEN_TCG_V6_vasrw(SHORTCODE) \ > @@ -478,7 +474,7 @@ static inline void assert_vhist_tmp(DisasContext *ctx) > TCGv shift = tcg_temp_new(); \ > tcg_gen_andi_tl(shift, RtV, 31); \ > tcg_gen_gvec_sars_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off, \ > - shift, sizeof(MMVector), sizeof(MMVector)); \ > + shift, VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ > } while (0) > > #define fGEN_TCG_V6_vasrw_acc(SHORTCODE) \ > @@ -487,10 +483,10 @@ static inline void assert_vhist_tmp(DisasContext *ctx) > TCGv shift = tcg_temp_new(); \ > tcg_gen_andi_tl(shift, RtV, 31); \ > tcg_gen_gvec_sars_var(MO_32, tcg_env, tmpoff, VuV_base, VuV_off, \ > - shift, sizeof(MMVector), sizeof(MMVector)); \ > + shift, VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ > tcg_gen_gvec_add_var(MO_32, VxV_base, VxV_off, VxV_base, VxV_off, \ > - tcg_env, tmpoff, sizeof(MMVector), \ > - sizeof(MMVector)); \ > + tcg_env, tmpoff, VECTOR_SIZE_BYTE, \ > + VECTOR_SIZE_BYTE); \ > } while (0) > > #define fGEN_TCG_V6_vlsrb(SHORTCODE) \ > @@ -498,7 +494,7 @@ static inline void assert_vhist_tmp(DisasContext *ctx) > TCGv shift = tcg_temp_new(); \ > tcg_gen_andi_tl(shift, RtV, 7); \ > tcg_gen_gvec_shrs_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, \ > - shift, sizeof(MMVector), sizeof(MMVector)); \ > + shift, VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ > } while (0) > > #define fGEN_TCG_V6_vlsrh(SHORTCODE) \ > @@ -506,7 +502,7 @@ static inline void assert_vhist_tmp(DisasContext *ctx) > TCGv shift = tcg_temp_new(); \ > tcg_gen_andi_tl(shift, RtV, 15); \ > tcg_gen_gvec_shrs_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ > - shift, sizeof(MMVector), sizeof(MMVector)); \ > + shift, VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ > } while (0) > > #define fGEN_TCG_V6_vlsrw(SHORTCODE) \ > @@ -514,7 +510,7 @@ static inline void assert_vhist_tmp(DisasContext *ctx) > TCGv shift = tcg_temp_new(); \ > tcg_gen_andi_tl(shift, RtV, 31); \ > tcg_gen_gvec_shrs_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off, \ > - shift, sizeof(MMVector), sizeof(MMVector)); \ > + shift, VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ > } while (0) > > /* Vector shift left - various forms */ > @@ -523,7 +519,7 @@ static inline void assert_vhist_tmp(DisasContext *ctx) > TCGv shift = tcg_temp_new(); \ > tcg_gen_andi_tl(shift, RtV, 7); \ > tcg_gen_gvec_shls_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, \ > - shift, sizeof(MMVector), sizeof(MMVector)); \ > + shift, VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ > } while (0) > > #define fGEN_TCG_V6_vaslh(SHORTCODE) \ > @@ -531,7 +527,7 @@ static inline void assert_vhist_tmp(DisasContext *ctx) > TCGv shift = tcg_temp_new(); \ > tcg_gen_andi_tl(shift, RtV, 15); \ > tcg_gen_gvec_shls_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ > - shift, sizeof(MMVector), sizeof(MMVector)); \ > + shift, VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ > } while (0) > > #define fGEN_TCG_V6_vaslh_acc(SHORTCODE) \ > @@ -540,10 +536,10 @@ static inline void assert_vhist_tmp(DisasContext *ctx) > TCGv shift = tcg_temp_new(); \ > tcg_gen_andi_tl(shift, RtV, 15); \ > tcg_gen_gvec_shls_var(MO_16, tcg_env, tmpoff, VuV_base, VuV_off, \ > - shift, sizeof(MMVector), sizeof(MMVector)); \ > + shift, VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ > tcg_gen_gvec_add_var(MO_16, VxV_base, VxV_off, VxV_base, VxV_off, \ > - tcg_env, tmpoff, sizeof(MMVector), \ > - sizeof(MMVector)); \ > + tcg_env, tmpoff, VECTOR_SIZE_BYTE, \ > + VECTOR_SIZE_BYTE); \ > } while (0) > > #define fGEN_TCG_V6_vaslw(SHORTCODE) \ > @@ -551,7 +547,7 @@ static inline void assert_vhist_tmp(DisasContext *ctx) > TCGv shift = tcg_temp_new(); \ > tcg_gen_andi_tl(shift, RtV, 31); \ > tcg_gen_gvec_shls_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off, \ > - shift, sizeof(MMVector), sizeof(MMVector)); \ > + shift, VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ > } while (0) > > #define fGEN_TCG_V6_vaslw_acc(SHORTCODE) \ > @@ -560,74 +556,74 @@ static inline void assert_vhist_tmp(DisasContext *ctx) > TCGv shift = tcg_temp_new(); \ > tcg_gen_andi_tl(shift, RtV, 31); \ > tcg_gen_gvec_shls_var(MO_32, tcg_env, tmpoff, VuV_base, VuV_off, \ > - shift, sizeof(MMVector), sizeof(MMVector)); \ > + shift, VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ > tcg_gen_gvec_add_var(MO_32, VxV_base, VxV_off, VxV_base, VxV_off, \ > - tcg_env, tmpoff, sizeof(MMVector), \ > - sizeof(MMVector)); \ > + tcg_env, tmpoff, VECTOR_SIZE_BYTE, \ > + VECTOR_SIZE_BYTE); \ > } while (0) > > /* Vector max - various forms */ > #define fGEN_TCG_V6_vmaxw(SHORTCODE) \ > tcg_gen_gvec_smax_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off, \ > - VvV_base, VvV_off, sizeof(MMVector), \ > - sizeof(MMVector)) > + VvV_base, VvV_off, VECTOR_SIZE_BYTE, \ > + VECTOR_SIZE_BYTE) > #define fGEN_TCG_V6_vmaxh(SHORTCODE) \ > tcg_gen_gvec_smax_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ > - VvV_base, VvV_off, sizeof(MMVector), \ > - sizeof(MMVector)) > + VvV_base, VvV_off, VECTOR_SIZE_BYTE, \ > + VECTOR_SIZE_BYTE) > #define fGEN_TCG_V6_vmaxuh(SHORTCODE) \ > tcg_gen_gvec_umax_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ > - VvV_base, VvV_off, sizeof(MMVector), \ > - sizeof(MMVector)) > + VvV_base, VvV_off, VECTOR_SIZE_BYTE, \ > + VECTOR_SIZE_BYTE) > #define fGEN_TCG_V6_vmaxb(SHORTCODE) \ > tcg_gen_gvec_smax_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, \ > - VvV_base, VvV_off, sizeof(MMVector), \ > - sizeof(MMVector)) > + VvV_base, VvV_off, VECTOR_SIZE_BYTE, \ > + VECTOR_SIZE_BYTE) > #define fGEN_TCG_V6_vmaxub(SHORTCODE) \ > tcg_gen_gvec_umax_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, \ > - VvV_base, VvV_off, sizeof(MMVector), \ > - sizeof(MMVector)) > + VvV_base, VvV_off, VECTOR_SIZE_BYTE, \ > + VECTOR_SIZE_BYTE) > > /* Vector min - various forms */ > #define fGEN_TCG_V6_vminw(SHORTCODE) \ > tcg_gen_gvec_smin_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off, \ > - VvV_base, VvV_off, sizeof(MMVector), \ > - sizeof(MMVector)) > + VvV_base, VvV_off, VECTOR_SIZE_BYTE, \ > + VECTOR_SIZE_BYTE) > #define fGEN_TCG_V6_vminh(SHORTCODE) \ > tcg_gen_gvec_smin_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ > - VvV_base, VvV_off, sizeof(MMVector), \ > - sizeof(MMVector)) > + VvV_base, VvV_off, VECTOR_SIZE_BYTE, \ > + VECTOR_SIZE_BYTE) > #define fGEN_TCG_V6_vminuh(SHORTCODE) \ > tcg_gen_gvec_umin_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ > - VvV_base, VvV_off, sizeof(MMVector), \ > - sizeof(MMVector)) > + VvV_base, VvV_off, VECTOR_SIZE_BYTE, \ > + VECTOR_SIZE_BYTE) > #define fGEN_TCG_V6_vminb(SHORTCODE) \ > tcg_gen_gvec_smin_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, \ > - VvV_base, VvV_off, sizeof(MMVector), \ > - sizeof(MMVector)) > + VvV_base, VvV_off, VECTOR_SIZE_BYTE, \ > + VECTOR_SIZE_BYTE) > #define fGEN_TCG_V6_vminub(SHORTCODE) \ > tcg_gen_gvec_umin_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, \ > - VvV_base, VvV_off, sizeof(MMVector), \ > - sizeof(MMVector)) > + VvV_base, VvV_off, VECTOR_SIZE_BYTE, \ > + VECTOR_SIZE_BYTE) > > /* Vector logical ops */ > #define fGEN_TCG_V6_vxor(SHORTCODE) \ > tcg_gen_gvec_xor_var(MO_64, VdV_base, VdV_off, VuV_base, VuV_off, \ > - VvV_base, VvV_off, sizeof(MMVector), \ > - sizeof(MMVector)) > + VvV_base, VvV_off, VECTOR_SIZE_BYTE, \ > + VECTOR_SIZE_BYTE) > > #define fGEN_TCG_V6_vand(SHORTCODE) \ > tcg_gen_gvec_and_var(MO_64, VdV_base, VdV_off, VuV_base, VuV_off, \ > - VvV_base, VvV_off, sizeof(MMVector), \ > - sizeof(MMVector)) > + VvV_base, VvV_off, VECTOR_SIZE_BYTE, \ > + VECTOR_SIZE_BYTE) > > #define fGEN_TCG_V6_vor(SHORTCODE) \ > tcg_gen_gvec_or_var(MO_64, VdV_base, VdV_off, VuV_base, VuV_off, > VvV_base, \ > - VvV_off, sizeof(MMVector), sizeof(MMVector)) > + VvV_off, VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) > > #define fGEN_TCG_V6_vnot(SHORTCODE) \ > tcg_gen_gvec_not_var(MO_64, VdV_base, VdV_off, VuV_base, VuV_off, \ > - sizeof(MMVector), sizeof(MMVector)) > + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) > > /* Q register logical ops */ > #define fGEN_TCG_V6_pred_or(SHORTCODE) \ > @@ -659,8 +655,8 @@ static inline void assert_vhist_tmp(DisasContext *ctx) > do { \ > intptr_t tmpoff = offsetof(CPUHexagonState, vtmp); \ > tcg_gen_gvec_cmp_var(COND, TYPE, tcg_env, tmpoff, VuV_base, VuV_off, > \ > - VvV_base, VvV_off, sizeof(MMVector), \ > - sizeof(MMVector)); \ > + VvV_base, VvV_off, VECTOR_SIZE_BYTE, \ > + VECTOR_SIZE_BYTE); \ > vec_to_qvec(SIZE, QdV_base, QdV_off, tcg_env, tmpoff); \ > } while (0) > > @@ -690,8 +686,8 @@ static inline void assert_vhist_tmp(DisasContext *ctx) > intptr_t tmpoff = offsetof(CPUHexagonState, vtmp); \ > intptr_t qoff = offsetof(CPUHexagonState, qtmp); \ > tcg_gen_gvec_cmp_var(COND, TYPE, tcg_env, tmpoff, VuV_base, VuV_off, > \ > - VvV_base, VvV_off, sizeof(MMVector), \ > - sizeof(MMVector)); \ > + VvV_base, VvV_off, VECTOR_SIZE_BYTE, \ > + VECTOR_SIZE_BYTE); \ > vec_to_qvec(SIZE, tcg_env, qoff, tcg_env, tmpoff); \ > OP(MO_64, QxV_base, QxV_off, QxV_base, QxV_off, tcg_env, qoff, \ > sizeof(MMQReg), sizeof(MMQReg)); \ > @@ -762,29 +758,29 @@ static inline void assert_vhist_tmp(DisasContext *ctx) > > /* Vector splat - various forms */ > #define fGEN_TCG_V6_lvsplatw(SHORTCODE) \ > - tcg_gen_gvec_dup_i32_var(MO_32, VdV_base, VdV_off, sizeof(MMVector), \ > - sizeof(MMVector), RtV) > + tcg_gen_gvec_dup_i32_var(MO_32, VdV_base, VdV_off, VECTOR_SIZE_BYTE, \ > + VECTOR_SIZE_BYTE, RtV) > > #define fGEN_TCG_V6_lvsplath(SHORTCODE) \ > - tcg_gen_gvec_dup_i32_var(MO_16, VdV_base, VdV_off, sizeof(MMVector), \ > - sizeof(MMVector), RtV) > + tcg_gen_gvec_dup_i32_var(MO_16, VdV_base, VdV_off, VECTOR_SIZE_BYTE, \ > + VECTOR_SIZE_BYTE, RtV) > > #define fGEN_TCG_V6_lvsplatb(SHORTCODE) \ > - tcg_gen_gvec_dup_i32_var(MO_8, VdV_base, VdV_off, sizeof(MMVector), \ > - sizeof(MMVector), RtV) > + tcg_gen_gvec_dup_i32_var(MO_8, VdV_base, VdV_off, VECTOR_SIZE_BYTE, \ > + VECTOR_SIZE_BYTE, RtV) > > /* Vector absolute value - various forms */ > #define fGEN_TCG_V6_vabsb(SHORTCODE) \ > tcg_gen_gvec_abs_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, \ > - sizeof(MMVector), sizeof(MMVector)) > + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) > > #define fGEN_TCG_V6_vabsh(SHORTCODE) \ > tcg_gen_gvec_abs_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ > - sizeof(MMVector), sizeof(MMVector)) > + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) > > #define fGEN_TCG_V6_vabsw(SHORTCODE) \ > tcg_gen_gvec_abs_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off, \ > - sizeof(MMVector), sizeof(MMVector)) > + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) > > /* Vector loads */ > #define fGEN_TCG_V6_vL32b_pi(SHORTCODE) SHORTCODE > @@ -826,12 +822,12 @@ static inline void assert_vhist_tmp(DisasContext *ctx) > fGEN_TCG_PRED_VEC_LOAD(fLSBOLD(PvV), \ > fEA_REG(RxV), \ > VdV, \ > - fPM_I(RxV, siV * sizeof(MMVector))) > + fPM_I(RxV, siV * VECTOR_SIZE_BYTE)) > #define fGEN_TCG_PRED_VEC_LOAD_npred_pi \ > fGEN_TCG_PRED_VEC_LOAD(fLSBOLDNOT(PvV), \ > fEA_REG(RxV), \ > VdV, \ > - fPM_I(RxV, siV * sizeof(MMVector))) > + fPM_I(RxV, siV * VECTOR_SIZE_BYTE)) > > #define fGEN_TCG_V6_vL32b_pred_pi(SHORTCODE) \ > fGEN_TCG_PRED_VEC_LOAD_pred_pi > @@ -860,12 +856,12 @@ static inline void assert_vhist_tmp(DisasContext *ctx) > > #define fGEN_TCG_PRED_VEC_LOAD_pred_ai \ > fGEN_TCG_PRED_VEC_LOAD(fLSBOLD(PvV), \ > - fEA_RI(RtV, siV * sizeof(MMVector)), \ > + fEA_RI(RtV, siV * VECTOR_SIZE_BYTE), \ > VdV, \ > do {} while (0)) > #define fGEN_TCG_PRED_VEC_LOAD_npred_ai \ > fGEN_TCG_PRED_VEC_LOAD(fLSBOLDNOT(PvV), \ > - fEA_RI(RtV, siV * sizeof(MMVector)), \ > + fEA_RI(RtV, siV * VECTOR_SIZE_BYTE), \ > VdV, \ > do {} while (0)) > > @@ -950,7 +946,7 @@ static inline void assert_vhist_tmp(DisasContext *ctx) > } while (0) > > #define fGEN_TCG_NEWVAL_VEC_STORE_pi \ > - fGEN_TCG_NEWVAL_VEC_STORE(fEA_REG(RxV), fPM_I(RxV, siV * > sizeof(MMVector))) > + fGEN_TCG_NEWVAL_VEC_STORE(fEA_REG(RxV), fPM_I(RxV, siV * > VECTOR_SIZE_BYTE)) > > #define fGEN_TCG_V6_vS32b_new_pi(SHORTCODE) \ > fGEN_TCG_NEWVAL_VEC_STORE_pi > @@ -958,7 +954,7 @@ static inline void assert_vhist_tmp(DisasContext *ctx) > fGEN_TCG_NEWVAL_VEC_STORE_pi > > #define fGEN_TCG_NEWVAL_VEC_STORE_ai \ > - fGEN_TCG_NEWVAL_VEC_STORE(fEA_RI(RtV, siV * sizeof(MMVector)), \ > + fGEN_TCG_NEWVAL_VEC_STORE(fEA_RI(RtV, siV * VECTOR_SIZE_BYTE), \ > do { } while (0)) > > #define fGEN_TCG_V6_vS32b_new_ai(SHORTCODE) \ > @@ -992,22 +988,22 @@ static inline void assert_vhist_tmp(DisasContext *ctx) > fGEN_TCG_PRED_VEC_STORE(fLSBOLD(PvV), \ > fEA_REG(RxV), \ > VsV, ALIGN, \ > - fPM_I(RxV, siV * sizeof(MMVector))) > + fPM_I(RxV, siV * VECTOR_SIZE_BYTE)) > #define fGEN_TCG_PRED_VEC_STORE_npred_pi(ALIGN) \ > fGEN_TCG_PRED_VEC_STORE(fLSBOLDNOT(PvV), \ > fEA_REG(RxV), \ > VsV, ALIGN, \ > - fPM_I(RxV, siV * sizeof(MMVector))) > + fPM_I(RxV, siV * VECTOR_SIZE_BYTE)) > #define fGEN_TCG_PRED_VEC_STORE_new_pred_pi \ > fGEN_TCG_PRED_VEC_STORE(fLSBOLD(PvV), \ > fEA_REG(RxV), \ > OsN, true, \ > - fPM_I(RxV, siV * sizeof(MMVector))) > + fPM_I(RxV, siV * VECTOR_SIZE_BYTE)) > #define fGEN_TCG_PRED_VEC_STORE_new_npred_pi \ > fGEN_TCG_PRED_VEC_STORE(fLSBOLDNOT(PvV), \ > fEA_REG(RxV), \ > OsN, true, \ > - fPM_I(RxV, siV * sizeof(MMVector))) > + fPM_I(RxV, siV * VECTOR_SIZE_BYTE)) > > #define fGEN_TCG_V6_vS32b_pred_pi(SHORTCODE) \ > fGEN_TCG_PRED_VEC_STORE_pred_pi(true) > @@ -1032,22 +1028,22 @@ static inline void assert_vhist_tmp(DisasContext *ctx) > > #define fGEN_TCG_PRED_VEC_STORE_pred_ai(ALIGN) \ > fGEN_TCG_PRED_VEC_STORE(fLSBOLD(PvV), \ > - fEA_RI(RtV, siV * sizeof(MMVector)), \ > + fEA_RI(RtV, siV * VECTOR_SIZE_BYTE), \ > VsV, ALIGN, \ > do { } while (0)) > #define fGEN_TCG_PRED_VEC_STORE_npred_ai(ALIGN) \ > fGEN_TCG_PRED_VEC_STORE(fLSBOLDNOT(PvV), \ > - fEA_RI(RtV, siV * sizeof(MMVector)), \ > + fEA_RI(RtV, siV * VECTOR_SIZE_BYTE), \ > VsV, ALIGN, \ > do { } while (0)) > #define fGEN_TCG_PRED_VEC_STORE_new_pred_ai \ > fGEN_TCG_PRED_VEC_STORE(fLSBOLD(PvV), \ > - fEA_RI(RtV, siV * sizeof(MMVector)), \ > + fEA_RI(RtV, siV * VECTOR_SIZE_BYTE), \ > OsN, true, \ > do { } while (0)) > #define fGEN_TCG_PRED_VEC_STORE_new_npred_ai \ > fGEN_TCG_PRED_VEC_STORE(fLSBOLDNOT(PvV), \ > - fEA_RI(RtV, siV * sizeof(MMVector)), \ > + fEA_RI(RtV, siV * VECTOR_SIZE_BYTE), \ > OsN, true, \ > do { } while (0)) > > diff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h > index 74c277fc06f..2bf360dd2c1 100644 > --- a/target/hexagon/mmvec/macros.h > +++ b/target/hexagon/mmvec/macros.h > @@ -221,7 +221,7 @@ > #define SCATTER_OP_WRITE_TO_MEM(TYPE) \ > do { \ > ra = GETPC(); \ > - for (int i = 0; i < sizeof(MMVector); i += sizeof(TYPE)) { \ > + for (int i = 0; i < MAX_VEC_SIZE_BYTES; i += sizeof(TYPE)) { \ > if (test_bit(i, env->vtcm_log.mask)) { \ > TYPE dst = 0; \ > TYPE inc = 0; \ > @@ -244,7 +244,7 @@ > } while (0) > #define SCATTER_OP_PROBE_MEM(TYPE, MMU_IDX, RETADDR) \ > do { \ > - for (int i = 0; i < sizeof(MMVector); i += sizeof(TYPE)) { \ > + for (int i = 0; i < MAX_VEC_SIZE_BYTES; i += sizeof(TYPE)) { \ > if (test_bit(i, env->vtcm_log.mask)) { \ > for (int j = 0; j < sizeof(TYPE); j++) { \ > probe_read(env, env->vtcm_log.va[i + j], 1, \ > @@ -329,8 +329,8 @@ > #endif > #define fVFOREACH(WIDTH, VAR) for (VAR = 0; VAR < fVELEM(WIDTH); VAR++) > #define fVARRAY_ELEMENT_ACCESS(ARRAY, TYPE, INDEX) \ > - ARRAY.v[(INDEX) / (fVECSIZE() / (sizeof(ARRAY.TYPE[0])))].TYPE[(INDEX) % > \ > - (fVECSIZE() / (sizeof(ARRAY.TYPE[0])))] > + ARRAY.v[(INDEX) / (fVECSIZE() / (sizeof(ARRAY.v[0].TYPE[0])))] \ > + .TYPE[(INDEX) % (fVECSIZE() / (sizeof(ARRAY.v[0].TYPE[0])))] > > #define fVSATDW(U, V) fVSATW(((((long long)U) << 32) | fZXTN(32, 64, V))) > #define fVASL_SATHI(U, V) fVSATW(((U) << 1) | ((V) >> 31)) > diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c > index cd4ae2f6838..845854f7bb7 100644 > --- a/target/hexagon/genptr.c > +++ b/target/hexagon/genptr.c > @@ -1508,9 +1508,9 @@ static void gen_vreg_load(DisasContext *ctx, TCGv_ptr > dstbase, > { > TCGv_i64 tmp = tcg_temp_new_i64(); > if (aligned) { > - tcg_gen_andi_tl(src, src, ~((int32_t)sizeof(MMVector) - 1)); > + tcg_gen_andi_tl(src, src, ~((int32_t)MAX_VEC_SIZE_BYTES - 1)); > } > - for (int i = 0; i < sizeof(MMVector) / 8; i++) { > + for (int i = 0; i < MAX_VEC_SIZE_BYTES / 8; i++) { > tcg_gen_qemu_ld_i64(tmp, src, ctx->mem_idx, MO_LE | MO_UQ); > tcg_gen_addi_tl(src, src, 8); > tcg_gen_st_i64(tmp, dstbase, dstoff + i * 8); > @@ -1532,15 +1532,15 @@ static void gen_vreg_store(DisasContext *ctx, TCGv > EA, TCGv_ptr srcbase, > tcg_gen_movi_tl(hex_vstore_pending[slot], 1); > if (aligned) { > tcg_gen_andi_tl(hex_vstore_addr[slot], EA, > - ~((int32_t)sizeof(MMVector) - 1)); > + ~((int32_t)MAX_VEC_SIZE_BYTES - 1)); > } else { > tcg_gen_mov_tl(hex_vstore_addr[slot], EA); > } > - tcg_gen_movi_tl(hex_vstore_size[slot], sizeof(MMVector)); > + tcg_gen_movi_tl(hex_vstore_size[slot], MAX_VEC_SIZE_BYTES); > > /* Copy the data to the vstore buffer */ > tcg_gen_gvec_mov_var(MO_64, tcg_env, dstoff, srcbase, srcoff, > - sizeof(MMVector), sizeof(MMVector)); > + MAX_VEC_SIZE_BYTES, MAX_VEC_SIZE_BYTES); > /* Set the mask to all 1's */ > tcg_gen_gvec_dup_imm(MO_64, maskoff, sizeof(MMQReg), sizeof(MMQReg), > ~0LL); > } > @@ -1555,12 +1555,12 @@ static void gen_vreg_masked_store(DisasContext *ctx, > TCGv EA, > > tcg_gen_movi_tl(hex_vstore_pending[slot], 1); > tcg_gen_andi_tl(hex_vstore_addr[slot], EA, > - ~((int32_t)sizeof(MMVector) - 1)); > - tcg_gen_movi_tl(hex_vstore_size[slot], sizeof(MMVector)); > + ~((int32_t)MAX_VEC_SIZE_BYTES - 1)); > + tcg_gen_movi_tl(hex_vstore_size[slot], MAX_VEC_SIZE_BYTES); > > /* Copy the data to the vstore buffer */ > tcg_gen_gvec_mov_var(MO_64, tcg_env, dstoff, srcbase, srcoff, > - sizeof(MMVector), sizeof(MMVector)); > + MAX_VEC_SIZE_BYTES, MAX_VEC_SIZE_BYTES); > /* Copy the mask */ > tcg_gen_gvec_mov_var(MO_64, tcg_env, maskoff, bitsbase, bitsoff, > sizeof(MMQReg), sizeof(MMQReg)); > @@ -1580,7 +1580,7 @@ static void vec_to_qvec(size_t size, TCGv_ptr dstbase, > intptr_t dstoff, > TCGv_i64 zero = tcg_constant_i64(0); > TCGv_i64 ones = tcg_constant_i64(~0); > > - for (int i = 0; i < sizeof(MMVector) / 8; i++) { > + for (int i = 0; i < MAX_VEC_SIZE_BYTES / 8; i++) { > tcg_gen_ld_i64(tmp, srcbase, srcoff + i * 8); > tcg_gen_movi_i64(mask, 0); > > diff --git a/target/hexagon/mmvec/system_ext_mmvec.c > b/target/hexagon/mmvec/system_ext_mmvec.c > index 081cadd814a..3777f68d6e7 100644 > --- a/target/hexagon/mmvec/system_ext_mmvec.c > +++ b/target/hexagon/mmvec/system_ext_mmvec.c > @@ -21,15 +21,13 @@ > > void mem_gather_store(CPUHexagonState *env, target_ulong vaddr, int slot) > { > - size_t size = sizeof(MMVector); > - > env->vstore_pending[slot] = 1; > env->vstore[slot].va = vaddr; > - env->vstore[slot].size = size; > - memcpy(&env->vstore[slot].data, &env->tmp_VRegs[0], size); > + env->vstore[slot].size = MAX_VEC_SIZE_BYTES; > + memcpy(&env->vstore[slot].data, &env->tmp_VRegs[0], MAX_VEC_SIZE_BYTES); > > /* On a gather store, overwrite the store mask to emulate dropped > gathers */ > - bitmap_copy(env->vstore[slot].mask, env->vtcm_log.mask, size); > + bitmap_copy(env->vstore[slot].mask, env->vtcm_log.mask, > MAX_VEC_SIZE_BYTES); > } > > void mem_vector_scatter_init(CPUHexagonState *env) > diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c > index 4f00ca773f3..4d948d548bc 100644 > --- a/target/hexagon/op_helper.c > +++ b/target/hexagon/op_helper.c > @@ -191,7 +191,7 @@ void HELPER(commit_hvx_stores)(CPUHexagonState *env) > g_assert_not_reached(); > } > } else { > - for (int i = 0; i < sizeof(MMVector); i++) { > + for (int i = 0; i < MAX_VEC_SIZE_BYTES; i++) { > if (test_bit(i, env->vtcm_log.mask)) { > cpu_stb_data_ra(env, env->vtcm_log.va[i], > > hexagon_mmvec_get_byte(&env->vtcm_log.data, > @@ -491,7 +491,7 @@ static void probe_hvx_stores(CPUHexagonState *env, int > mmu_idx, > g_assert_not_reached(); > } > } else { > - for (int i = 0; i < sizeof(MMVector); i++) { > + for (int i = 0; i < MAX_VEC_SIZE_BYTES; i++) { > if (test_bit(i, env->vtcm_log.mask)) { > probe_write(env, env->vtcm_log.va[i], 1, mmu_idx, > retaddr); > } > @@ -1408,14 +1408,14 @@ void HELPER(vhist)(CPUHexagonState *env) > MMVector *input = &env->tmp_VRegs[0]; > > for (int lane = 0; lane < 8; lane++) { > - for (int i = 0; i < sizeof(MMVector) / 8; ++i) { > + for (int i = 0; i < MAX_VEC_SIZE_BYTES / 8; ++i) { > unsigned char value = hexagon_mmvec_get_byte(input, > - (sizeof(MMVector) / 8) * lane + i); > + (MAX_VEC_SIZE_BYTES / 8) * lane + i); > unsigned char regno = value >> 3; > unsigned char element = value & 7; > > hex_hvx(env)->VRegs[regno] > - .uh[(sizeof(MMVector) / 16) * lane + element]++; > + .uh[(MAX_VEC_SIZE_BYTES / 16) * lane + element]++; > } > } > } > @@ -1425,15 +1425,15 @@ void HELPER(vhistq)(CPUHexagonState *env) > MMVector *input = &env->tmp_VRegs[0]; > > for (int lane = 0; lane < 8; lane++) { > - for (int i = 0; i < sizeof(MMVector) / 8; ++i) { > + for (int i = 0; i < MAX_VEC_SIZE_BYTES / 8; ++i) { > unsigned char value = hexagon_mmvec_get_byte(input, > - (sizeof(MMVector) / 8) * lane + i); > + (MAX_VEC_SIZE_BYTES / 8) * lane + i); > unsigned char regno = value >> 3; > unsigned char element = value & 7; > > - if (fGETQBIT(env->qtmp, sizeof(MMVector) / 8 * lane + i)) { > + if (fGETQBIT(env->qtmp, MAX_VEC_SIZE_BYTES / 8 * lane + i)) { > hex_hvx(env)->VRegs[regno].uh[ > - (sizeof(MMVector) / 16) * lane + element]++; > + (MAX_VEC_SIZE_BYTES / 16) * lane + element]++; > } > } > } > @@ -1443,7 +1443,7 @@ void HELPER(vwhist256)(CPUHexagonState *env) > { > MMVector *input = &env->tmp_VRegs[0]; > > - for (int i = 0; i < (sizeof(MMVector) / 2); i++) { > + for (int i = 0; i < (MAX_VEC_SIZE_BYTES / 2); i++) { > unsigned int bucket = fGETUBYTE(0, input->h[i]); > unsigned int weight = fGETUBYTE(1, input->h[i]); > unsigned int vindex = (bucket >> 3) & 0x1F; > @@ -1458,7 +1458,7 @@ void HELPER(vwhist256q)(CPUHexagonState *env) > { > MMVector *input = &env->tmp_VRegs[0]; > > - for (int i = 0; i < (sizeof(MMVector) / 2); i++) { > + for (int i = 0; i < (MAX_VEC_SIZE_BYTES / 2); i++) { > unsigned int bucket = fGETUBYTE(0, input->h[i]); > unsigned int weight = fGETUBYTE(1, input->h[i]); > unsigned int vindex = (bucket >> 3) & 0x1F; > @@ -1475,7 +1475,7 @@ void HELPER(vwhist256_sat)(CPUHexagonState *env) > { > MMVector *input = &env->tmp_VRegs[0]; > > - for (int i = 0; i < (sizeof(MMVector) / 2); i++) { > + for (int i = 0; i < (MAX_VEC_SIZE_BYTES / 2); i++) { > unsigned int bucket = fGETUBYTE(0, input->h[i]); > unsigned int weight = fGETUBYTE(1, input->h[i]); > unsigned int vindex = (bucket >> 3) & 0x1F; > @@ -1490,7 +1490,7 @@ void HELPER(vwhist256q_sat)(CPUHexagonState *env) > { > MMVector *input = &env->tmp_VRegs[0]; > > - for (int i = 0; i < (sizeof(MMVector) / 2); i++) { > + for (int i = 0; i < (MAX_VEC_SIZE_BYTES / 2); i++) { > unsigned int bucket = fGETUBYTE(0, input->h[i]); > unsigned int weight = fGETUBYTE(1, input->h[i]); > unsigned int vindex = (bucket >> 3) & 0x1F; > @@ -1507,7 +1507,7 @@ void HELPER(vwhist128)(CPUHexagonState *env) > { > MMVector *input = &env->tmp_VRegs[0]; > > - for (int i = 0; i < (sizeof(MMVector) / 2); i++) { > + for (int i = 0; i < (MAX_VEC_SIZE_BYTES / 2); i++) { > unsigned int bucket = fGETUBYTE(0, input->h[i]); > unsigned int weight = fGETUBYTE(1, input->h[i]); > unsigned int vindex = (bucket >> 3) & 0x1F; > @@ -1522,7 +1522,7 @@ void HELPER(vwhist128q)(CPUHexagonState *env) > { > MMVector *input = &env->tmp_VRegs[0]; > > - for (int i = 0; i < (sizeof(MMVector) / 2); i++) { > + for (int i = 0; i < (MAX_VEC_SIZE_BYTES / 2); i++) { > unsigned int bucket = fGETUBYTE(0, input->h[i]); > unsigned int weight = fGETUBYTE(1, input->h[i]); > unsigned int vindex = (bucket >> 3) & 0x1F; > @@ -1539,7 +1539,7 @@ void HELPER(vwhist128m)(CPUHexagonState *env, int32_t > uiV) > { > MMVector *input = &env->tmp_VRegs[0]; > > - for (int i = 0; i < (sizeof(MMVector) / 2); i++) { > + for (int i = 0; i < (MAX_VEC_SIZE_BYTES / 2); i++) { > unsigned int bucket = fGETUBYTE(0, input->h[i]); > unsigned int weight = fGETUBYTE(1, input->h[i]); > unsigned int vindex = (bucket >> 3) & 0x1F; > @@ -1556,7 +1556,7 @@ void HELPER(vwhist128qm)(CPUHexagonState *env, int32_t > uiV) > { > MMVector *input = &env->tmp_VRegs[0]; > > - for (int i = 0; i < (sizeof(MMVector) / 2); i++) { > + for (int i = 0; i < (MAX_VEC_SIZE_BYTES / 2); i++) { > unsigned int bucket = fGETUBYTE(0, input->h[i]); > unsigned int weight = fGETUBYTE(1, input->h[i]); > unsigned int vindex = (bucket >> 3) & 0x1F;
It seems that this patch do different kind of changes, and uses various values: - keep sizeof(MMVector) is some macros (?), like fGEN_TCG_PAIR_ADDSUB_BASIC. - use MAX_VEC_SIZE_BYTES - use VECTOR_SIZE_BYTE What's the difference between those cases? Regards, Pierrick
