On Wed, 23 Sept 2026 at 22:56, Manuele Conti <[email protected]> wrote: > > RM0090 7.3.1/7.3.3: HSERDY follows HSEON, PLLRDY follows PLLON and > SWS follows SW. Upstream stored raw values, so firmware polling for > ready or checking SWS never saw the expected state. > > Mirror enable bits into ready bits on CR writes and SW into SWS on > CFGR writes. Clock switching is instantaneous in QEMU. No oscillator > startup or PLL lock delay is modelled. > > Add qtest writing HSEON/PLLON/SW and checking HSERDY/PLLRDY/SWS, > including clearing again on HSEOFF/PLLOFF. > > Signed-off-by: Manuele Conti <[email protected]> > --- > hw/misc/stm32_rcc.c | 18 ++++++++++ > tests/qtest/meson.build | 3 +- > tests/qtest/stm32f405-rcc-test.c | 57 ++++++++++++++++++++++++++++++++ > 3 files changed, 77 insertions(+), 1 deletion(-) > create mode 100644 tests/qtest/stm32f405-rcc-test.c > > diff --git a/hw/misc/stm32_rcc.c b/hw/misc/stm32_rcc.c > index 5cfb39e560..ba64a87bdd 100644 > --- a/hw/misc/stm32_rcc.c > +++ b/hw/misc/stm32_rcc.c > @@ -90,6 +90,24 @@ static void stm32_rcc_write(void *opaque, hwaddr addr, > } > > switch (addr) { > + case STM32_RCC_CR: > + /* > + * Oscillators become ready immediately in QEMU. > + * Mirror enable bits into ready bits: HSEON->HSERDY, > + * PLLON->PLLRDY. See RM0090 7.3.1. > + */ > + value = deposit32(value, 17, 1, extract32(value, 16, 1)); > + value = deposit32(value, 25, 1, extract32(value, 24, 1));
The manual says that also bit 27 is the RDY flag for bit 26 (PLLI2SON) and bit 1 is the RDY flag for bit 0 (HSION). I think we should make those also follow their ON bits while we're here. Otherwise this change looks good. thanks -- PMM
