Expose the hexagon event_name[] array via a hexagon_event_name() helper and register it as the CPUClass::exception_name() handler, so the common exception logging can resolve Hexagon exception codes to names.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]> --- target/hexagon/cpu_bits.h | 2 ++ target/hexagon/cpu.c | 37 +++++++++++++++++++++++++++++++++++++ target/hexagon/hexswi.c | 30 +----------------------------- 3 files changed, 40 insertions(+), 29 deletions(-) diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h index a8fba4aa188..7d1bdfcbc71 100644 --- a/target/hexagon/cpu_bits.h +++ b/target/hexagon/cpu_bits.h @@ -61,6 +61,8 @@ enum hex_event { HEX_EVENT_INTF = 0x1f, }; +const char *hexagon_event_name(int event); + enum hex_cause { HEX_CAUSE_NONE = -1, HEX_CAUSE_RESET = 0x000, diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 1f7d8a8df70..be286b1f2ee 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -318,6 +318,42 @@ void hexagon_debug(CPUHexagonState *env) hexagon_dump(env, stdout, CPU_DUMP_FPU); } +const char *hexagon_event_name(int event) +{ + static const char *event_name[] = { + [HEX_EVENT_RESET] = "HEX_EVENT_RESET", + [HEX_EVENT_IMPRECISE] = "HEX_EVENT_IMPRECISE", + [HEX_EVENT_PRECISE] = "HEX_EVENT_PRECISE", + [HEX_EVENT_TLB_MISS_X] = "HEX_EVENT_TLB_MISS_X", + [HEX_EVENT_TLB_MISS_RW] = "HEX_EVENT_TLB_MISS_RW", + [HEX_EVENT_TRAP0] = "HEX_EVENT_TRAP0", + [HEX_EVENT_TRAP1] = "HEX_EVENT_TRAP1", + [HEX_EVENT_FPTRAP] = "HEX_EVENT_FPTRAP", + [HEX_EVENT_DEBUG] = "HEX_EVENT_DEBUG", + [HEX_EVENT_INT0] = "HEX_EVENT_INT0", + [HEX_EVENT_INT1] = "HEX_EVENT_INT1", + [HEX_EVENT_INT2] = "HEX_EVENT_INT2", + [HEX_EVENT_INT3] = "HEX_EVENT_INT3", + [HEX_EVENT_INT4] = "HEX_EVENT_INT4", + [HEX_EVENT_INT5] = "HEX_EVENT_INT5", + [HEX_EVENT_INT6] = "HEX_EVENT_INT6", + [HEX_EVENT_INT7] = "HEX_EVENT_INT7", + [HEX_EVENT_INT8] = "HEX_EVENT_INT8", + [HEX_EVENT_INT9] = "HEX_EVENT_INT9", + [HEX_EVENT_INTA] = "HEX_EVENT_INTA", + [HEX_EVENT_INTB] = "HEX_EVENT_INTB", + [HEX_EVENT_INTC] = "HEX_EVENT_INTC", + [HEX_EVENT_INTD] = "HEX_EVENT_INTD", + [HEX_EVENT_INTE] = "HEX_EVENT_INTE", + [HEX_EVENT_INTF] = "HEX_EVENT_INTF", + }; + + if (event < 0 || event >= ARRAY_SIZE(event_name) || !event_name[event]) { + return "unknown"; + } + return event_name[event]; +} + static void hexagon_cpu_set_pc(CPUState *cs, vaddr value) { cpu_env(cs)->gpr[HEX_REG_PC] = value; @@ -826,6 +862,7 @@ static void hexagon_cpu_class_init(ObjectClass *c, const void *data) &mcc->parent_phases); cc->class_by_name = hexagon_cpu_class_by_name; + cc->exception_name = hexagon_event_name; cc->dump_state = hexagon_dump_state; cc->set_pc = hexagon_cpu_set_pc; cc->get_pc = hexagon_cpu_get_pc; diff --git a/target/hexagon/hexswi.c b/target/hexagon/hexswi.c index 4705e915aea..be366d7a373 100644 --- a/target/hexagon/hexswi.c +++ b/target/hexagon/hexswi.c @@ -729,34 +729,6 @@ static void set_addresses(CPUHexagonState *env, uint32_t pc_offset, env->gpr[HEX_REG_PC] = evb | (exception_index << 2); } -static const char *event_name[] = { - [HEX_EVENT_RESET] = "HEX_EVENT_RESET", - [HEX_EVENT_IMPRECISE] = "HEX_EVENT_IMPRECISE", - [HEX_EVENT_PRECISE] = "HEX_EVENT_PRECISE", - [HEX_EVENT_TLB_MISS_X] = "HEX_EVENT_TLB_MISS_X", - [HEX_EVENT_TLB_MISS_RW] = "HEX_EVENT_TLB_MISS_RW", - [HEX_EVENT_TRAP0] = "HEX_EVENT_TRAP0", - [HEX_EVENT_TRAP1] = "HEX_EVENT_TRAP1", - [HEX_EVENT_FPTRAP] = "HEX_EVENT_FPTRAP", - [HEX_EVENT_DEBUG] = "HEX_EVENT_DEBUG", - [HEX_EVENT_INT0] = "HEX_EVENT_INT0", - [HEX_EVENT_INT1] = "HEX_EVENT_INT1", - [HEX_EVENT_INT2] = "HEX_EVENT_INT2", - [HEX_EVENT_INT3] = "HEX_EVENT_INT3", - [HEX_EVENT_INT4] = "HEX_EVENT_INT4", - [HEX_EVENT_INT5] = "HEX_EVENT_INT5", - [HEX_EVENT_INT6] = "HEX_EVENT_INT6", - [HEX_EVENT_INT7] = "HEX_EVENT_INT7", - [HEX_EVENT_INT8] = "HEX_EVENT_INT8", - [HEX_EVENT_INT9] = "HEX_EVENT_INT9", - [HEX_EVENT_INTA] = "HEX_EVENT_INTA", - [HEX_EVENT_INTB] = "HEX_EVENT_INTB", - [HEX_EVENT_INTC] = "HEX_EVENT_INTC", - [HEX_EVENT_INTD] = "HEX_EVENT_INTD", - [HEX_EVENT_INTE] = "HEX_EVENT_INTE", - [HEX_EVENT_INTF] = "HEX_EVENT_INTF" -}; - void hexagon_cpu_do_interrupt(CPUState *cs) { @@ -769,7 +741,7 @@ void hexagon_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "\t%s: event 0x%02x:%s, cause 0x%" PRIx32 "(%" PRIu32 ")\n", __func__, (unsigned)cs->exception_index, - event_name[cs->exception_index], env->cause_code, + hexagon_event_name(cs->exception_index), env->cause_code, env->cause_code); env->llsc_addr = ~0; -- 2.55.0
