Hi Peter, On Wed, Oct 7, 2026 at 4:41 PM Peter Maydell <[email protected]> wrote: > > On Sun, 4 Oct 2026 at 10:05, Bin Meng <[email protected]> wrote: > > > > U-Boot's shared i.MX6 identification code reads PERIPHBASE + 0x4 on > > MCIMX6UL-EVK. The first private peripheral page is currently unmapped, > > so that access causes a data abort before the console is ready. > > > > The GIC-400 register map reserves offsets 0x0000 through 0x0fff and > > specifies read-as-zero, write-ignored accesses to reserved locations. > > Model that page in the private peripheral device. > > > > Reference: GIC-400 TRM (ARM DDI 0471B), sections 3.1 and 3.2 > > https://documentation-service.arm.com/static/5e8f15e27100066a414f7424 > > The Cortex-A15's internal GIC isn't a GIC-400, as far as I know.
The Linux kernel says it is a GIC-400 on i.MX6UL https://github.com/torvalds/linux/blob/master/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi#L158 intc: interrupt-controller@a01000 { compatible = "arm,gic-400", "arm,cortex-a7-gic"; > > > Signed-off-by: Bin Meng <[email protected]> > > RAZ/WI doesn't match the documented behaviour of the Cortex-A15 > for this region in its TRM: > > https://support.arm.com/documentation/ddi0438/i/generic-interrupt-controller/gic-functional-description/gic-memory-map?lang=en > > "Read access to reserved regions results in a Data Abort exception to > the requesting processor. Write access to reserved regions results in > the assertion of nINTERRIRQ." > It seems the A15 manual and GIC-400 manual are contradictory. I am not sure how to proceed. Regards, Bin
