Factor openrisc_excp_name() out of openrisc_cpu_do_interrupt() and register it as the CPUClass::exception_name() handler, so the common exception logging can resolve OpenRISC exception codes to names.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]> --- target/or1k/cpu.h | 2 ++ target/or1k/cpu.c | 1 + target/or1k/exception.c | 24 ++++++++++++++++++++++++ target/or1k/interrupt.c | 19 +------------------ 4 files changed, 28 insertions(+), 18 deletions(-) diff --git a/target/or1k/cpu.h b/target/or1k/cpu.h index fc4387ce7ae..96ed1779fae 100644 --- a/target/or1k/cpu.h +++ b/target/or1k/cpu.h @@ -155,6 +155,8 @@ enum { EXCP_NR, }; +const char *openrisc_excp_name(int excp); + /* Supervisor register */ enum { SR_SM = (1 << 0), diff --git a/target/or1k/cpu.c b/target/or1k/cpu.c index 66c00c0930c..e15f6bb5e71 100644 --- a/target/or1k/cpu.c +++ b/target/or1k/cpu.c @@ -285,6 +285,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, const void *data) &occ->parent_phases); cc->class_by_name = openrisc_cpu_class_by_name; + cc->exception_name = openrisc_excp_name; cc->dump_state = openrisc_cpu_dump_state; cc->set_pc = openrisc_cpu_set_pc; cc->get_pc = openrisc_cpu_get_pc; diff --git a/target/or1k/exception.c b/target/or1k/exception.c index 0479a069592..388bf6dbab8 100644 --- a/target/or1k/exception.c +++ b/target/or1k/exception.c @@ -22,6 +22,30 @@ #include "cpu.h" #include "exception.h" +const char *openrisc_excp_name(int excp) +{ + static const char * const excp_name[EXCP_NR] = { + [EXCP_RESET] = "RESET", + [EXCP_BUSERR] = "BUSERR (bus error)", + [EXCP_DPF] = "DFP (data protection fault)", + [EXCP_IPF] = "IPF (code protection fault)", + [EXCP_TICK] = "TICK (timer interrupt)", + [EXCP_ALIGN] = "ALIGN", + [EXCP_ILLEGAL] = "ILLEGAL", + [EXCP_INT] = "INT (device interrupt)", + [EXCP_DTLBMISS] = "DTLBMISS (data tlb miss)", + [EXCP_ITLBMISS] = "ITLBMISS (code tlb miss)", + [EXCP_RANGE] = "RANGE", + [EXCP_SYSCALL] = "SYSCALL", + [EXCP_FPE] = "FPE", + [EXCP_TRAP] = "TRAP", + }; + if (excp < 0 || excp >= ARRAY_SIZE(excp_name) || !excp_name[excp]) { + return "(unknown)"; + } + return excp_name[excp]; +} + G_NORETURN void raise_exception(OpenRISCCPU *cpu, uint32_t excp) { CPUState *cs = CPU(cpu); diff --git a/target/or1k/interrupt.c b/target/or1k/interrupt.c index 6e89157639a..399c98e3881 100644 --- a/target/or1k/interrupt.c +++ b/target/or1k/interrupt.c @@ -66,26 +66,9 @@ void openrisc_cpu_do_interrupt(CPUState *cs) } if (exception > 0 && exception < EXCP_NR) { - static const char * const int_name[EXCP_NR] = { - [EXCP_RESET] = "RESET", - [EXCP_BUSERR] = "BUSERR (bus error)", - [EXCP_DPF] = "DFP (data protection fault)", - [EXCP_IPF] = "IPF (code protection fault)", - [EXCP_TICK] = "TICK (timer interrupt)", - [EXCP_ALIGN] = "ALIGN", - [EXCP_ILLEGAL] = "ILLEGAL", - [EXCP_INT] = "INT (device interrupt)", - [EXCP_DTLBMISS] = "DTLBMISS (data tlb miss)", - [EXCP_ITLBMISS] = "ITLBMISS (code tlb miss)", - [EXCP_RANGE] = "RANGE", - [EXCP_SYSCALL] = "SYSCALL", - [EXCP_FPE] = "FPE", - [EXCP_TRAP] = "TRAP", - }; - qemu_log_mask(CPU_LOG_INT, "CPU: %d INT: %s\n", cs->cpu_index, - int_name[exception]); + openrisc_excp_name(exception)); hwaddr vect_pc = exception << 8; if (env->cpucfgr & CPUCFGR_EVBARP) { -- 2.55.0
