Hi Gustavo,
On Thu, 08 Oct 2026 17:40:27 +0100, Gustavo Romero <[email protected]> wrote:
[...]
> RAM_BASE is precisely defined as 1 << 30 because the way we link the tests
> based
> on the memory layout defined in tests/tcg/aarch64/system/kernel.ld, right?
Yes. The tables are static, so they're linked a few MB above RAM_BASE,
inside the blocks both stages map at RAM_BASE (and stage 2 again at
HIGH_IPA | RAM_BASE).
> That's the bit that also confused me, like, how Stage 2 entries:
>
> s2_l2[RAM_BASE >> 29] = RAM_BASE | S2_BLOCK;
> s2_l2_high[RAM_BASE >> 29] = RAM_BASE | S2_BLOCK
>
> are taking us back to s1_l0. How s1_l0 ends up related to RAM_BASE :)
>
> Hence, I think it's worth mentioning that relationship also in this text. How
> about something like:
>
> "RAM_BASE is chosen to match the memory layout defined in kernel.ld. As a
> result, s1_l0 resides at an offset from RAM_BASE after linking."
>
> Wdyt?
Agree. The stage 1 and VTCR.DS stage 2 mappings depend on it too, so
I've put it on the RAM_BASE define for v3 rather than in that comment:
/*
* kernel.ld links the test at 1GB, so the tables below lie within the
* blocks mapped at RAM_BASE.
*/
#define RAM_BASE 0x40000000UL
Cheers,
/fuad
