[PATCH v3 13/14] target/riscv: Clear virtualization mode on reset

[TANG Tiancheng]

Reset enters M-mode without clearing virt_enabled, leaving an invalid
M-mode, V=1 state after a reset from virtual mode. Clear virt_enabled
alongside the privilege reset.

Fixes: ef6bb7b62682 ("target/riscv: Add the virtulisation mode")
Reviewed-by: Daniel Henrique Barboza <daniel.barb...@oss.qualcomm.com>
Signed-off-by: TANG Tiancheng <lyn...@linux.alibaba.com>
---
 target/riscv/cpu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 
da4c1a090b9b74c5b11dac94987fe573cc1aed5c..34422d0204e7c1532c3424626c70d33f805833d5
 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -980,6 +980,7 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType 
type)
 #ifndef CONFIG_USER_ONLY
     env->misa_mxl = mcc->def->misa_mxl_max;
     env->priv = PRV_M;
+    env->virt_enabled = false;
     env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
     if (env->misa_mxl > MXL_RV32) {
         /*

-- 
2.43.0