On Fri, 9 Oct 2026 at 12:57, Fuad Tabba <[email protected]> wrote: > > Hi folks, > > Changes since v2 [1]: > - Each fix is now followed by its own test, and the test description > moved from the commit message into the file header. (Gustavo) > - Clarified the stage 2 comment in the test. (Gustavo) > - Noted that RAM_BASE matches the address kernel.ld links the test > at. (Gustavo) > - Collected Reviewed-by from Gustavo on all patches. (thanks!) > > Two fixes to how get_phys_addr_lpae() forms the initial table base > address when TTBR uses its 52-bit layout, each followed by a TCG test. > > The first stops TTBR[5:4] leaking into the base address of a table > smaller than 64 bytes. KVM's page_fault_test hangs on it under TCG in > its 16KB, 52-bit PA guest mode. Itaru reported the 16KB hang on kvmarm > last year [2]. > > The second uses the 52-bit layout whenever TCR.DS is set, as the > architecture does, where QEMU used it only with a 52-bit OA. With a > smaller OA a non-zero TTBR[5:2] is then an Address size fault. > > Based on QEMU master (f7ada39eda). > > Cheers, > /fuad > > [1] https://lore.kernel.org/r/[email protected] > [2] https://lore.kernel.org/r/[email protected] > > Fuad Tabba (4): > target/arm: Clear TTBR[5:0] from a 52-bit table base address > tests/tcg/aarch64: Add a test for a two-entry 52-bit TTBR table > target/arm: Use the 52-bit TTBR base address layout when TCR.DS is set > tests/tcg/aarch64: Test the TTBR layout with TCR.DS and a 48-bit OA
Applied to target-arm.next, thanks. -- PMM
