On Tue, 13 Oct 2026 at 11:07, Philippe Mathieu-Daudé <[email protected]> wrote: > > On 7/5/26 17:51, Peter Maydell wrote: > > The GICv5 PPI pending status is handled by two registers, one of > > which is write-1-to-set and one of which is write-1-to-clear. The > > pending state is read-only for PPIs where the handling mode is Edge. > > > > Signed-off-by: Peter Maydell <[email protected]> > > Reviewed-by: Jonathan Cameron <[email protected]> > > Message-id: [email protected] > > --- > > target/arm/cpu.h | 1 + > > target/arm/tcg/gicv5-cpuif.c | 44 ++++++++++++++++++++++++++++++++++++ > > 2 files changed, 45 insertions(+) > > > > static const ARMCPRegInfo gicv5_cpuif_reginfo[] = { > > /* > > * Barrier: wait until the effects of a cpuif system register > > @@ -314,6 +334,30 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = { > > .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_hm[1]), > > .resetvalue = PPI_HMR1_RESET, > > }, > > + { .name = "ICC_PPI_CPENDR0_EL1", .state = ARM_CP_STATE_AA64, > > + .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 13, .opc2 = 4, > > + .access = PL1_RW, .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, > > + .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_pend[0]), > > + .writefn = gic_ppi_cpend_write, > > + }, > > + { .name = "ICC_PPI_CPENDR1_EL1", .state = ARM_CP_STATE_AA64, > > + .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 13, .opc2 = 5, > > + .access = PL1_RW, .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, > > + .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_pend[1]), > > + .writefn = gic_ppi_cpend_write, > > + }, > > + { .name = "ICC_PPI_SPENDR0_EL1", .state = ARM_CP_STATE_AA64, > > + .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 13, .opc2 = 6, > > + .access = PL1_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW, > > + .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_pend[0]), > > + .writefn = gic_ppi_spend_write, > > + }, > > + { .name = "ICC_PPI_SPENDR0_EL1", .state = ARM_CP_STATE_AA64, > > ICC_PPI_SPENDR1_EL1 typo?
Yep; no visible effect as these regs aren't exposed to the gdbstub. I'll send a patch. -- PMM
