[PATCH] target/arm/tcg/gicv5-cpuif: Fix typo in ICC_PPI_SPENDR1_EL1 name

[Peter Maydell]

A cut-and-paste error meant that the cpreg for ICC_PPI_SPENDR1_EL1
incorrectly named it SPENDR0; as these regs aren't exposed to gdb the
string here is for debug only, so this has no visible consquences,
but it's confusing.  Fix the error.

Fixes: 585dad9e79e1 ("target/arm: GICv5 cpuif: Implement PPI pending status 
registers")
Reported-by: Philippe Mathieu-Daudé <phi...@oss.qualcomm.com>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
---
 target/arm/tcg/gicv5-cpuif.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c
index a6e6c440849..e847fc722b9 100644
--- a/target/arm/tcg/gicv5-cpuif.c
+++ b/target/arm/tcg/gicv5-cpuif.c
@@ -893,7 +893,7 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {
         .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_pend[0]),
         .writefn = gic_ppi_spend_write,
     },
-    {   .name = "ICC_PPI_SPENDR0_EL1", .state = ARM_CP_STATE_AA64,
+    {   .name = "ICC_PPI_SPENDR1_EL1", .state = ARM_CP_STATE_AA64,
         .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 13, .opc2 = 7,
         .access = PL1_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW,
         .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_pend[1]),
-- 
2.43.0