Re: [PATCH v5 20/23] target/loongarch: translate LVZ guest TLB instructions

[Bibo Mao]

On 2026/10/9 上午11:05, SignKirigami wrote:
Decode, disassemble and translate GTLBSRCH, GTLBRD, GTLBWR, GTLBFILL,
GTLBCLR and GTLBFLUSH for host LVZ execution.

Signed-off-by: SignKirigami <prc...@krgm.moe>
Signed-off-by: Hengyu Yu <yuhengy...@mails.ucas.ac.cn>
---
  target/loongarch/disas.c                      |  6 ++
  target/loongarch/insns.decode                 |  7 +++
  .../tcg/insn_trans/trans_privileged.c.inc     | 60 +++++++++++++++++++
  3 files changed, 73 insertions(+)

diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 2436c9eec3..6425dea17c 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -700,6 +700,12 @@ INSN(tlbfill,      empty)
  INSN(tlbclr,       empty)
  INSN(tlbflush,     empty)
  INSN(invtlb,       i_rr)
+INSN(gtlbclr,      empty)
+INSN(gtlbflush,    empty)
+INSN(gtlbsrch,     empty)
+INSN(gtlbrd,       empty)
+INSN(gtlbwr,       empty)
+INSN(gtlbfill,     empty)
  INSN(cacop,        cop_r_i)
  INSN(lddir,        rr_i)
  INSN(ldpte,        j_i)
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 4612af9433..cbcc30c31f 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -499,6 +499,13 @@ bgeu            0110 11 ................ ..... .....     
@rr_offs16
    gcsrxchg          0000 0101 .............. ..... .....     @rr_csr
  }
  
+gtlbclr          0000 01100100 10000 01000 00000 00001    @empty
+gtlbflush        0000 01100100 10000 01001 00000 00001    @empty
+gtlbsrch         0000 01100100 10000 01010 00000 00001    @empty
+gtlbrd           0000 01100100 10000 01011 00000 00001    @empty
+gtlbwr           0000 01100100 10000 01100 00000 00001    @empty
+gtlbfill         0000 01100100 10000 01101 00000 00001    @empty
This series instruction for gtlbxxx is not used by KVM, I suggest 
removing these instruction. It make things complicated.

Regards
Bibo Mao
+
  iocsrrd_b        0000 01100100 10000 00000 ..... .....    @rr
  iocsrrd_h        0000 01100100 10000 00001 ..... .....    @rr
  iocsrrd_w        0000 01100100 10000 00010 ..... .....    @rr
diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc 
b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
index 37b7ef13dc..ae481aa83f 100644
--- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
+++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
@@ -42,6 +42,12 @@ GEN_FALSE_TRANS(idle)
  GEN_FALSE_TRANS(gcsrrd)
  GEN_FALSE_TRANS(gcsrwr)
  GEN_FALSE_TRANS(gcsrxchg)
+GEN_FALSE_TRANS(gtlbclr)
+GEN_FALSE_TRANS(gtlbflush)
+GEN_FALSE_TRANS(gtlbsrch)
+GEN_FALSE_TRANS(gtlbrd)
+GEN_FALSE_TRANS(gtlbwr)
+GEN_FALSE_TRANS(gtlbfill)
  
  #else
  
@@ -339,6 +345,15 @@ static bool trans_tlbsrch(DisasContext *ctx, arg_tlbsrch *a)
      return true;
  }
  
+static bool trans_gtlbsrch(DisasContext *ctx, arg_gtlbsrch *a)
+{
+    if (check_plv(ctx) || !avail_LVZ(ctx) || is_guest_mmu_idx(ctx->mem_idx)) {
+        return false;
+    }
+    gen_helper_tlbsrch(tcg_env, tcg_constant_i32(1));
+    return true;
+}
+
  static bool trans_tlbrd(DisasContext *ctx, arg_tlbrd *a)
  {
      if (check_plv(ctx)) {
@@ -393,6 +408,51 @@ static bool trans_tlbflush(DisasContext *ctx, arg_tlbflush 
*a)
      return true;
  }
  
+static bool trans_gtlbrd(DisasContext *ctx, arg_gtlbrd *a)
+{
+    if (check_plv(ctx) || !avail_LVZ(ctx) || is_guest_mmu_idx(ctx->mem_idx)) {
+        return false;
+    }
+    gen_helper_tlbrd(tcg_env, tcg_constant_i32(1));
+    return true;
+}
+
+static bool trans_gtlbwr(DisasContext *ctx, arg_gtlbwr *a)
+{
+    if (check_plv(ctx) || !avail_LVZ(ctx) || is_guest_mmu_idx(ctx->mem_idx)) {
+        return false;
+    }
+    gen_helper_tlbwr(tcg_env, tcg_constant_i32(1));
+    return true;
+}
+
+static bool trans_gtlbfill(DisasContext *ctx, arg_gtlbfill *a)
+{
+    if (check_plv(ctx) || !avail_LVZ(ctx) || is_guest_mmu_idx(ctx->mem_idx)) {
+        return false;
+    }
+    gen_helper_tlbfill(tcg_env, tcg_constant_i32(1));
+    return true;
+}
+
+static bool trans_gtlbclr(DisasContext *ctx, arg_gtlbclr *a)
+{
+    if (check_plv(ctx) || !avail_LVZ(ctx) || is_guest_mmu_idx(ctx->mem_idx)) {
+        return false;
+    }
+    gen_helper_tlbclr(tcg_env, tcg_constant_i32(1));
+    return true;
+}
+
+static bool trans_gtlbflush(DisasContext *ctx, arg_gtlbflush *a)
+{
+    if (check_plv(ctx) || !avail_LVZ(ctx) || is_guest_mmu_idx(ctx->mem_idx)) {
+        return false;
+    }
+    gen_helper_tlbflush(tcg_env, tcg_constant_i32(1));
+    return true;
+}
+
  static bool trans_invtlb(DisasContext *ctx, arg_invtlb *a)
  {
      TCGv rj = gpr_src(ctx, a->rj, EXT_NONE);