From: Jamin Lin <[email protected]> The ASPEED device ID enum has grown over time without a consistent ordering rule. This makes it difficult to determine where new device IDs should be added and reduces readability and maintainability as more devices are introduced.
Sort the device IDs alphabetically to provide a consistent ordering rule. Keep related numbered devices together, such as SPI0, SPI1 and SPI2. No functional change. Signed-off-by: Jamin Lin <[email protected]> Reviewed-by: Cédric Le Goater <[email protected]> Link: https://lore.kernel.org/qemu-devel/[email protected] Signed-off-by: Cédric Le Goater <[email protected]> --- include/hw/arm/aspeed_soc.h | 176 ++++++++++++++++++------------------ 1 file changed, 88 insertions(+), 88 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 38226d9b8049..a11038574338 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -195,64 +195,56 @@ struct AspeedSoCClass { }; enum { - ASPEED_DEV_VBOOTROM, - ASPEED_DEV_SPI_BOOT, - ASPEED_DEV_IOMEM, - ASPEED_DEV_IOMEM0, - ASPEED_DEV_IOMEM1, - ASPEED_DEV_UART0, - ASPEED_DEV_UART1, - ASPEED_DEV_UART2, - ASPEED_DEV_UART3, - ASPEED_DEV_UART4, - ASPEED_DEV_UART5, - ASPEED_DEV_UART6, - ASPEED_DEV_UART7, - ASPEED_DEV_UART8, - ASPEED_DEV_UART9, - ASPEED_DEV_UART10, - ASPEED_DEV_UART11, - ASPEED_DEV_UART12, - ASPEED_DEV_UART13, - ASPEED_DEV_VUART, - ASPEED_DEV_FMC, - ASPEED_DEV_SPI0, - ASPEED_DEV_SPI1, - ASPEED_DEV_SPI2, + ASPEED_DEV_ACRY, + ASPEED_DEV_ADC, + ASPEED_DEV_DP, + ASPEED_DEV_DPMCU, ASPEED_DEV_EHCI1, ASPEED_DEV_EHCI2, ASPEED_DEV_EHCI3, ASPEED_DEV_EHCI4, - ASPEED_DEV_VIC, - ASPEED_DEV_INTC, - ASPEED_DEV_INTCIO, - ASPEED_DEV_SDMC, - ASPEED_DEV_SCU, - ASPEED_DEV_ADC, - ASPEED_DEV_SBC, + ASPEED_DEV_EMMC, ASPEED_DEV_EMMC_BC, - ASPEED_DEV_VIDEO, - ASPEED_DEV_SRAM0, - ASPEED_DEV_SRAM1, - ASPEED_DEV_SDHCI, + ASPEED_DEV_ESPI, + ASPEED_DEV_ETH1, + ASPEED_DEV_ETH2, + ASPEED_DEV_ETH3, + ASPEED_DEV_ETH4, + ASPEED_DEV_FMC, + ASPEED_DEV_FSI1, + ASPEED_DEV_FSI2, ASPEED_DEV_GPIO, ASPEED_DEV_GPIO_1_8V, - ASPEED_DEV_SGPIOM0, - ASPEED_DEV_SGPIOM1, - ASPEED_DEV_RTC, - ASPEED_DEV_TIMER1, - ASPEED_DEV_TIMER2, - ASPEED_DEV_TIMER3, - ASPEED_DEV_TIMER4, - ASPEED_DEV_TIMER5, - ASPEED_DEV_TIMER6, - ASPEED_DEV_TIMER7, - ASPEED_DEV_TIMER8, - ASPEED_DEV_WDT, - ASPEED_DEV_PWM, - ASPEED_DEV_LPC, - ASPEED_DEV_IBT, + ASPEED_DEV_HACE, ASPEED_DEV_I2C, + ASPEED_DEV_I3C, + ASPEED_DEV_IBT, + ASPEED_DEV_INTC, + ASPEED_DEV_INTCIO, + ASPEED_DEV_IOMEM, + ASPEED_DEV_IOMEM0, + ASPEED_DEV_IOMEM1, + ASPEED_DEV_IOEXP0_I2C, + ASPEED_DEV_IOEXP1_I2C, + ASPEED_DEV_IOEXP0_I3C, + ASPEED_DEV_IOEXP1_I3C, + ASPEED_DEV_IOEXP0_INTCIO, + ASPEED_DEV_IOEXP1_INTCIO, + ASPEED_DEV_IPC0, + ASPEED_DEV_IPC1, + ASPEED_DEV_JTAG0, + ASPEED_DEV_JTAG1, + ASPEED_DEV_KCS, + ASPEED_DEV_LPC, + ASPEED_DEV_LTPI_CTRL1, + ASPEED_DEV_LTPI_CTRL2, + ASPEED_DEV_LTPI_IO0, + ASPEED_DEV_LTPI_IO1, + ASPEED_DEV_MII1, + ASPEED_DEV_MII2, + ASPEED_DEV_MII3, + ASPEED_DEV_MII4, + ASPEED_DEV_OTP, ASPEED_DEV_PCIE0, ASPEED_DEV_PCIE1, ASPEED_DEV_PCIE2, @@ -263,49 +255,57 @@ enum { ASPEED_DEV_PCIE_MMIO1, ASPEED_DEV_PCIE_MMIO2, ASPEED_DEV_PECI, - ASPEED_DEV_ETH1, - ASPEED_DEV_ETH2, - ASPEED_DEV_ETH3, - ASPEED_DEV_ETH4, - ASPEED_DEV_MII1, - ASPEED_DEV_MII2, - ASPEED_DEV_MII3, - ASPEED_DEV_MII4, - ASPEED_DEV_SDRAM, - ASPEED_DEV_XDMA, - ASPEED_DEV_EMMC, - ASPEED_DEV_KCS, - ASPEED_DEV_HACE, - ASPEED_DEV_ACRY, - ASPEED_DEV_DPMCU, - ASPEED_DEV_DP, - ASPEED_DEV_I3C, - ASPEED_DEV_ESPI, - ASPEED_DEV_UDC, - ASPEED_DEV_JTAG0, - ASPEED_DEV_JTAG1, - ASPEED_DEV_FSI1, - ASPEED_DEV_FSI2, + ASPEED_DEV_PRIC0, + ASPEED_DEV_PRIC1, + ASPEED_DEV_PWM, + ASPEED_DEV_RTC, + ASPEED_DEV_SBC, + ASPEED_DEV_SCU, ASPEED_DEV_SCUIO, + ASPEED_DEV_SDHCI, + ASPEED_DEV_SDMC, + ASPEED_DEV_SDRAM, + ASPEED_DEV_SGPIOM0, + ASPEED_DEV_SGPIOM1, ASPEED_DEV_SLI, ASPEED_DEV_SLIIO, + ASPEED_DEV_SPI_BOOT, + ASPEED_DEV_SPI0, + ASPEED_DEV_SPI1, + ASPEED_DEV_SPI2, + ASPEED_DEV_SRAM0, + ASPEED_DEV_SRAM1, + ASPEED_DEV_TIMER1, + ASPEED_DEV_TIMER2, + ASPEED_DEV_TIMER3, + ASPEED_DEV_TIMER4, + ASPEED_DEV_TIMER5, + ASPEED_DEV_TIMER6, + ASPEED_DEV_TIMER7, + ASPEED_DEV_TIMER8, + ASPEED_DEV_UART0, + ASPEED_DEV_UART1, + ASPEED_DEV_UART2, + ASPEED_DEV_UART3, + ASPEED_DEV_UART4, + ASPEED_DEV_UART5, + ASPEED_DEV_UART6, + ASPEED_DEV_UART7, + ASPEED_DEV_UART8, + ASPEED_DEV_UART9, + ASPEED_DEV_UART10, + ASPEED_DEV_UART11, + ASPEED_DEV_UART12, + ASPEED_DEV_UART13, + ASPEED_DEV_UDC, + ASPEED_DEV_VBOOTROM, + ASPEED_DEV_VIC, + ASPEED_DEV_VIDEO, + ASPEED_DEV_VUART, + ASPEED_DEV_WDT, + ASPEED_DEV_XDMA, ASPEED_GIC_DIST, ASPEED_GIC_REDIST, - ASPEED_DEV_IPC0, - ASPEED_DEV_IPC1, - ASPEED_DEV_LTPI_CTRL1, - ASPEED_DEV_LTPI_CTRL2, - ASPEED_DEV_LTPI_IO0, - ASPEED_DEV_LTPI_IO1, - ASPEED_DEV_IOEXP0_I2C, - ASPEED_DEV_IOEXP1_I2C, - ASPEED_DEV_IOEXP0_INTCIO, - ASPEED_DEV_IOEXP1_INTCIO, - ASPEED_DEV_IOEXP0_I3C, - ASPEED_DEV_IOEXP1_I3C, - ASPEED_DEV_PRIC0, - ASPEED_DEV_PRIC1, - ASPEED_DEV_OTP, }; const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types); -- 2.56.0
