Smaller pullreq this time around; FEAT_IDTE3 plus a scattering of bug fixes.
-- PMM The following changes since commit 7e8d3c7fc460fe7cd28a3e423d7466fa292bc269: Merge tag 'pull-aspeed-20261015' of https://github.com/legoater/qemu into staging (2026-10-15 14:58:28 +0200) are available in the Git repository at: https://gitlab.com/pm215/qemu.git tags/pull-target-arm-20261015 for you to fetch changes up to c595a87dc3e318532460c654c36dea08e6ac993a: target/arm/tcg/gicv5-cpuif: Fix typo in ICC_PPI_SPENDR1_EL1 name (2026-10-15 17:38:38 +0100) ---------------------------------------------------------------- target-arm queue: * fix user-mode emulation of ID_AA64MMFR0_EL1 * Fix handling of 52-bit TTBRs * Emulate FEAT_IDTE3 * hw/arm/virt: Use TAG_GRANULE when creating tag memory * hw/timer/stm32f2xx_timer: fix periodic mode and CEN handling * hw/misc/stm32_rcc: Mirror clock ready and switch status bits * hw/intc/arm_gicv5: Make IRS_IDR0 reads return actual value, not 0 * target/arm/tcg/gicv5-cpuif: Fix typo in ICC_PPI_SPENDR1_EL1 name ---------------------------------------------------------------- Alex Bennée (1): target/arm: fix user-mode emulation of ID_AA64MMFR0_EL1 Fuad Tabba (4): target/arm: Clear TTBR[5:0] from a 52-bit table base address tests/tcg/aarch64: Add a test for a two-entry 52-bit TTBR table target/arm: Use the 52-bit TTBR base address layout when TCR.DS is set tests/tcg/aarch64: Test the TTBR layout with TCR.DS and a 48-bit OA Gustavo Romero (1): hw/arm/virt: Use TAG_GRANULE when creating tag memory Manuele Conti (2): hw/timer/stm32f2xx_timer: fix periodic mode and CEN handling hw/misc/stm32_rcc: Mirror clock ready and switch status bits Peter Maydell (2): hw/intc/arm_gicv5: Make IRS_IDR0 reads return actual value, not 0 target/arm/tcg/gicv5-cpuif: Fix typo in ICC_PPI_SPENDR1_EL1 name Richard Henderson (6): target/arm: Rename isar_feature_aa64_idst target/arm: Enable writes to SCR_EL3.TID{3,5} target/arm: Squash accessfn in modify_arm_cp_regs_with_len target/arm: Implement SCR_EL3.TID3 target/arm: Implement SCR_EL3.TID5 target/arm: Enable FEAT_IDTE3 for -cpu max MAINTAINERS | 1 + docs/system/arm/emulation.rst | 1 + include/hw/timer/stm32f2xx_timer.h | 2 +- target/arm/cpu-features.h | 7 +- target/arm/cpu.h | 2 + hw/arm/virt.c | 6 +- hw/intc/arm_gicv5.c | 1 + hw/misc/stm32_rcc.c | 19 ++++ hw/timer/stm32f2xx_timer.c | 73 +++++++++--- target/arm/helper.c | 51 ++++++++- target/arm/ptw.c | 18 ++- target/arm/tcg/cpu64.c | 4 + target/arm/tcg/gicv5-cpuif.c | 2 +- target/arm/tcg/op_helper.c | 2 +- target/arm/tcg/translate-a64.c | 2 +- tests/qtest/stm32f405-rcc-test.c | 62 ++++++++++ tests/qtest/stm32f405-timer-test.c | 136 ++++++++++++++++++++++ tests/tcg/aarch64/sysregs.c | 31 ++++- tests/tcg/aarch64/system/ttbr-baddr.c | 208 ++++++++++++++++++++++++++++++++++ tests/qtest/meson.build | 2 + tests/tcg/aarch64/system/meson.build | 6 + 21 files changed, 596 insertions(+), 40 deletions(-) create mode 100644 tests/qtest/stm32f405-rcc-test.c create mode 100644 tests/qtest/stm32f405-timer-test.c create mode 100644 tests/tcg/aarch64/system/ttbr-baddr.c
