Now that both targets and semihosting implementation both use the semihosting ops interface, we can remove all common_* functions. This allows us to link together the three targets concerned: arm, hexagon and riscv.
Reviewed-by: Brian Cain <[email protected]> Reviewed-by: Philippe Mathieu-Daudé <[email protected]> Link: https://lore.kernel.org/qemu-devel/[email protected] Signed-off-by: Pierrick Bouvier <[email protected]> --- include/semihosting/common-semi.h | 7 ------ target/arm/common-semi-target.c | 35 ----------------------------- target/hexagon/common-semi-target.c | 35 ----------------------------- target/riscv/common-semi-target.c | 35 ----------------------------- 4 files changed, 112 deletions(-) diff --git a/include/semihosting/common-semi.h b/include/semihosting/common-semi.h index f0f8185d8e6..085192e0c86 100644 --- a/include/semihosting/common-semi.h +++ b/include/semihosting/common-semi.h @@ -53,12 +53,5 @@ typedef struct SemihostingCPUOps { void common_semi_cb(CPUState *cs, uint64_t ret, int err); void do_common_semihosting(CPUState *cs); -uint64_t common_semi_arg(CPUState *cs, int argno); -void common_semi_set_ret(CPUState *cs, uint64_t ret); -void common_semi_set_err(CPUState *cs, int err); -bool is_64bit_semihosting(CPUArchState *env); -bool common_semi_sys_exit_is_extended(CPUState *cs); -uint64_t common_semi_stack_bottom(CPUState *cs); -bool common_semi_has_synccache(CPUArchState *env); #endif /* COMMON_SEMI_H */ diff --git a/target/arm/common-semi-target.c b/target/arm/common-semi-target.c index dc5f277a59e..ab37730f3ef 100644 --- a/target/arm/common-semi-target.c +++ b/target/arm/common-semi-target.c @@ -71,38 +71,3 @@ const SemihostingCPUOps arm_semihosting_ops = { .stack_bottom = arm_semi_stack_bottom, .has_synccache = arm_semi_has_synccache, }; - -uint64_t common_semi_arg(CPUState *cs, int argno) -{ - return arm_semi_arg(cs, argno); -} - -void common_semi_set_ret(CPUState *cs, uint64_t ret) -{ - arm_semi_set_ret(cs, ret); -} - -void common_semi_set_err(CPUState *cs, int err) -{ - arm_semi_set_err(cs, err); -} - -bool is_64bit_semihosting(CPUArchState *env) -{ - return arm_semi_is_64bit(env_cpu(env)); -} - -bool common_semi_sys_exit_is_extended(CPUState *cs) -{ - return arm_semi_sys_exit_is_extended(cs); -} - -uint64_t common_semi_stack_bottom(CPUState *cs) -{ - return arm_semi_stack_bottom(cs); -} - -bool common_semi_has_synccache(CPUArchState *env) -{ - return arm_semi_has_synccache(env_cpu(env)); -} diff --git a/target/hexagon/common-semi-target.c b/target/hexagon/common-semi-target.c index da92ff298a2..a4c346eff2f 100644 --- a/target/hexagon/common-semi-target.c +++ b/target/hexagon/common-semi-target.c @@ -59,38 +59,3 @@ const SemihostingCPUOps hexagon_semihosting_ops = { .stack_bottom = hexagon_semi_stack_bottom, .has_synccache = hexagon_semi_has_synccache, }; - -uint64_t common_semi_arg(CPUState *cs, int argno) -{ - return hexagon_semi_arg(cs, argno); -} - -void common_semi_set_ret(CPUState *cs, uint64_t ret) -{ - hexagon_semi_set_ret(cs, ret); -} - -void common_semi_set_err(CPUState *cs, int err) -{ - hexagon_semi_set_err(cs, err); -} - -bool is_64bit_semihosting(CPUArchState *env) -{ - return hexagon_semi_is_64bit(env_cpu(env)); -} - -bool common_semi_sys_exit_is_extended(CPUState *cs) -{ - return hexagon_semi_sys_exit_is_extended(cs); -} - -uint64_t common_semi_stack_bottom(CPUState *cs) -{ - return hexagon_semi_stack_bottom(cs); -} - -bool common_semi_has_synccache(CPUArchState *env) -{ - return hexagon_semi_has_synccache(env_cpu(env)); -} diff --git a/target/riscv/common-semi-target.c b/target/riscv/common-semi-target.c index f0f9e29dc4c..44f29a82982 100644 --- a/target/riscv/common-semi-target.c +++ b/target/riscv/common-semi-target.c @@ -62,38 +62,3 @@ const SemihostingCPUOps riscv_semihosting_ops = { .stack_bottom = riscv_semi_stack_bottom, .has_synccache = riscv_semi_has_synccache, }; - -uint64_t common_semi_arg(CPUState *cs, int argno) -{ - return riscv_semi_arg(cs, argno); -} - -void common_semi_set_ret(CPUState *cs, uint64_t ret) -{ - riscv_semi_set_ret(cs, ret); -} - -void common_semi_set_err(CPUState *cs, int err) -{ - riscv_semi_set_err(cs, err); -} - -bool is_64bit_semihosting(CPUArchState *env) -{ - return riscv_semi_is_64bit(env_cpu(env)); -} - -bool common_semi_sys_exit_is_extended(CPUState *cs) -{ - return riscv_semi_sys_exit_is_extended(cs); -} - -uint64_t common_semi_stack_bottom(CPUState *cs) -{ - return riscv_semi_stack_bottom(cs); -} - -bool common_semi_has_synccache(CPUArchState *env) -{ - return riscv_semi_has_synccache(env_cpu(env)); -} -- 2.43.0
