On 10/14/2026 9:58 PM, Mohamed Mediouni wrote:
On 14. Oct 2026, at 21:52, Brian Cain <[email protected]> wrote:
v83 and v85 introduce new ISA extensions:
- CFI/restricted branches
- scalar atomic operations
Hi,
Probably not possible to emulate nicely but the TRM for those says:
V85 ERRATA: Atomicity may be lost if a competing instruction is not an atomic.
To guarantee atomicity, only atomic instructions should be used for the memory
location
I don't think we need to precisely emulate an erratum like this - but
I'll review it to see whether we're "too strong" or "not strong enough".
Given that is it expected to be used on v85? Or is it a footgun best unexposed
for that generation?
Great question - I will double check how widely these are used.
Would also note that the user-mode DMA spec is still behind the NDA wall, which
makes no sense whatsoever when everybody on the platform is using it anyway...
Yeah that's a shame but I think I've convinced Qualcomm to publish
them. So - standby.
- scalar float operations
- trap2 instruction
- vector stack, used by HLX
The HLX vector coprocessor, also introduced by these new revisions, is
not included in this series.
The cross-toolchain doesn't yet support these opcodes. So in our tests,
we've manually encoded the instructions using ".word" directives and we
invoke the tests with the explicit '-cpu'. The directives will be replaced
with the mnemonics and explicit '-cpu' removed once the assembler has the
necessary support. I expect LLVM 24.x will include these instructions.
Brian Cain (12):
target/hexagon: sort tag_rev_info entries by version
Hexagon: add v85 CPU model
hw/hexagon: add v85 machines
linux-user/hexagon: report ISA HWCAP through v85
target/hexagon: add v85 scalar atomics
target/hexagon: add v83 trap2 and vector stack instructions
target/hexagon: generate vector frame instructions with IDEF parser
target/hexagon: reject reserved L4_loadw_phys encoding from v83
target/hexagon: preserve callr target when Rs is LR
target/hexagon: implement control flow integrity (CFI)
target/hexagon: add vsf* instructions
tests/tcg/hexagon: add v85 scalar tests
docs/system/hexagon/emulation.rst | 2 +-
include/hw/hexagon/hexagon.h | 6 +-
linux-user/hexagon/target_elf.h | 2 +
target/hexagon/cpu-qom.h | 4 +
target/hexagon/cpu.h | 3 +
target/hexagon/cpu_bits.h | 2 +
target/hexagon/gen_tcg.h | 93 +++++++++++-
target/hexagon/gen_tcg_sys.h | 6 +
target/hexagon/genptr.h | 12 ++
target/hexagon/helper.h | 5 +
target/hexagon/hex_regs.h | 2 +
target/hexagon/idef-parser/parser-helpers.h | 1 +
target/hexagon/macros.h | 12 ++
target/hexagon/translate.h | 4 +
tests/tcg/hexagon/cfi_tgts.h | 16 ++
hw/hexagon/machine_cfg_v85na_1.h.inc | 50 +++++++
hw/hexagon/machine_cfg_v85qa_1.h.inc | 51 +++++++
target/hexagon/attribs_def.h.inc | 2 +
target/hexagon/reg_fields_def.h.inc | 1 +
hw/hexagon/hexagon_dsp.c | 48 +++++-
linux-user/hexagon/cpu_loop.c | 10 ++
linux-user/hexagon/elfload.c | 10 ++
target/hexagon/cpu.c | 10 +-
target/hexagon/decode.c | 5 +
target/hexagon/genptr.c | 95 +++++++++++-
target/hexagon/hex_interrupts.c | 3 +
target/hexagon/hexswi.c | 16 ++
target/hexagon/idef-parser/parser-helpers.c | 14 ++
target/hexagon/machine.c | 3 +-
target/hexagon/op_helper.c | 73 +++++++++
target/hexagon/translate.c | 53 ++++++-
tests/tcg/hexagon/atomics.c | 102 +++++++++++++
tests/tcg/hexagon/cfi_user.c | 63 ++++++++
tests/tcg/hexagon/check_rev_gating.c | 10 ++
tests/tcg/hexagon/invalid-encoding.c | 20 +++
tests/tcg/hexagon/trap2.c | 34 +++++
tests/tcg/hexagon/v83_scalar_fp.c | 98 ++++++++++++
tests/tcg/hexagon/vallocframe.c | 111 ++++++++++++++
target/hexagon/tag_rev_info.c.inc | 82 ++++++++--
target/hexagon/gen_idef_parser_funcs.py | 4 +-
target/hexagon/idef-parser/idef-parser.lex | 8 +
target/hexagon/idef-parser/idef-parser.y | 9 +-
target/hexagon/imported/alu.idef | 3 +
target/hexagon/imported/branch.idef | 38 +++++
target/hexagon/imported/encode_pp.def | 43 +++++-
target/hexagon/imported/encode_subinsn.def | 1 +
target/hexagon/imported/float.idef | 49 ++++++
target/hexagon/imported/ldst.idef | 15 ++
target/hexagon/imported/macros.def | 10 ++
target/hexagon/imported/subinsns.idef | 2 +
target/hexagon/imported/system.idef | 9 ++
tests/tcg/hexagon/cfi_tgts.S | 157 ++++++++++++++++++++
tests/tcg/hexagon/meson.build | 19 ++-
53 files changed, 1470 insertions(+), 31 deletions(-)
create mode 100644 tests/tcg/hexagon/cfi_tgts.h
create mode 100644 hw/hexagon/machine_cfg_v85na_1.h.inc
create mode 100644 hw/hexagon/machine_cfg_v85qa_1.h.inc
create mode 100644 tests/tcg/hexagon/cfi_user.c
create mode 100644 tests/tcg/hexagon/trap2.c
create mode 100644 tests/tcg/hexagon/v83_scalar_fp.c
create mode 100644 tests/tcg/hexagon/vallocframe.c
create mode 100644 tests/tcg/hexagon/cfi_tgts.S
--
2.34.1
