On 10/16/26 03:01, [email protected] wrote:
From: Alistair Francis<[email protected]>
The following changes since commit 7e8d3c7fc460fe7cd28a3e423d7466fa292bc269:
Merge tag 'pull-aspeed-20261015' ofhttps://github.com/legoater/qemu into
staging (2026-10-15 14:58:28 +0200)
are available in the Git repository at:
https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20261016
for you to fetch changes up to bfdd4f6a918ffad4f013d4f53a9adca1adc0aa3b:
target/riscv: normalize Zcmt jvt.mode on writes (2026-10-16 10:40:39 +1000)
----------------------------------------------------------------
RISC-V PR for 11.2
* Check G-stage write permission for VS-stage A/D updates
* Restore LCOFI handling in interrupt CSRs
* Fix csrrs disasembly decoding
* Stop translating after WFI
* Raise virtual instruction exception on svinval instructions
* Fix some KVM migration issues
* Add support for Milk-V Duo board
* Make MIP accesses atomic and BQL-safe
* Add initial sdext support
* Add SiFive Xsfvqmaccdod/Xsfvqmaccqoq int8 matmul extensions
* Add the Server Platform Reference Board
* Revert invalidate reservations after stores for linux user
* Fix the UART register width in SPCR
* Check Svnapot PTE before updating A/D bits
* Add Tenstorrent Atlantis PRCM model
* Fix RV32 fixed counter accesses
* Write back fsgnjn.h and fsgnjx.h results
* Ensure Zcmt jvt.mode is WARL
Applied, thanks.
r~
