Signed-off-by: Karthika B <[email protected]>
---
target/riscv/cpu-qom.h | 2 ++
target/riscv/cpu.c | 25 +++++++++++++++++++++++++
2 files changed, 27 insertions(+)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 30dcdcfaae..58abfef048 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -58,6 +58,8 @@
#define TYPE_RISCV_CPU_XIANGSHAN_KMH
RISCV_CPU_TYPE_NAME("xiangshan-kunminghu")
#define TYPE_RISCV_CPU_MIPS_P8700 RISCV_CPU_TYPE_NAME("mips-p8700")
#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
+#define TYPE_RISCV_CPU_VEGA32 RISCV_CPU_TYPE_NAME("vega32")
+#define TYPE_RISCV_CPU_VEGA64 RISCV_CPU_TYPE_NAME("vega64")
OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5903df9954..7b96b7b670 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2987,6 +2987,20 @@ static const TypeInfo riscv_cpu_type_infos[] = {
),
#endif
+
+#if defined(TARGET_RISCV32)
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_VEGA32, TYPE_RISCV_CPU_SIFIVE_U,
+ .misa_mxl_max = MXL_RV32,
+ .misa_ext = RVI | RVM | RVA | RVS | RVU,
+ .priv_spec = PRIV_VERSION_LATEST,
+
+ .cfg.max_satp_mode = VM_1_10_SV32,
+ .cfg.ext_zicsr = true,
+ .cfg.ext_zifencei = true,
+ .cfg.pmp = false,
+ ),
+#endif
+
#if (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY))
DEFINE_RISCV_CPU(TYPE_RISCV_CPU_MAX32, TYPE_RISCV_DYNAMIC_CPU,
.cfg.max_satp_mode = VM_1_10_SV32,
@@ -3032,6 +3046,17 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.misa_mxl_max = MXL_RV64,
),
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_VEGA64, TYPE_RISCV_CPU_SIFIVE_U,
+ .misa_mxl_max = MXL_RV64,
+ .misa_ext = RVI | RVM | RVA | RVS | RVU,
+ .priv_spec = PRIV_VERSION_LATEST,
+
+ .cfg.max_satp_mode = VM_1_10_SV39,
+ .cfg.ext_zicsr = true,
+ .cfg.ext_zifencei = true,
+ .cfg.pmp = false,
+ ),
+
DEFINE_RISCV_CPU(TYPE_RISCV_CPU_THEAD_C906, TYPE_RISCV_VENDOR_CPU,
.misa_mxl_max = MXL_RV64,
.misa_ext = RVG | RVC | RVS | RVU,
--
2.43.0
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