On 10/14/2026 2:05 PM, Pierrick Bouvier wrote: > This series makes hexagon compatible with the other ones we already > integrated. > > The biggest change is to introduce a semihosting interface, since existing arm > symbols conflict with hexagon ones. This is also need for when we'll integrate > riscv soon. > > v3 > -- > > - constify some semihosting operations (now taking a const *cs in parameter). > - edit commit description when using new interface in semihosting > implementation, to reflect we don't check if semi_ops is NULL. > > v2 > -- > > - rebase on top of master (one conflict with helper renaming) > > Note: this series is fully reviewed and I'll send it as PR on Friday if there > are no additional comments. > > Pierrick Bouvier (12): > target/hexagon: prefix helpers conflicting with other arch > target-info: add target_hexagon > hw/hexagon/virt: make machine available for hexagon target only > hw/core/cpu: restrict tcg_ops to CONFIG_TCG only > semihosting: declare semihosting cpu ops > target/riscv/cpu: constify cpu parameter for riscv_cpu_mxl > target/riscv: declare semihosting ops > target/hexagon: declare semihosting ops > target/arm: declare semihosting ops > semihosting: use new semihosting ops > semihosting: remove common_* functions > meson.build: add hexagon-softmmu to multi-target > > hw/hexagon/virt.c | 2 ++ > include/hw/core/cpu.h | 8 +++++ > include/qemu/target-info.h | 7 ++++ > include/semihosting/common-semi.h | 24 +++++++++---- > meson.build | 1 + > semihosting/arm-compat-semi.c | 56 ++++++++++++++--------------- > target-info.c | 5 +++ > target/arm/common-semi-target.c | 33 +++++++++++------ > target/arm/cpu.c | 4 +++ > target/arm/internals.h | 2 ++ > target/hexagon/common-semi-target.c | 30 ++++++++++------ > target/hexagon/cpu.c | 2 ++ > target/hexagon/gen_tcg.h | 2 +- > target/hexagon/gen_tcg_sys.h | 2 +- > target/hexagon/helper.h | 4 +-- > target/hexagon/hex_mmu.c | 2 +- > target/hexagon/hex_mmu.h | 2 +- > target/hexagon/internal.h | 2 ++ > target/hexagon/op_helper.c | 4 +-- > target/hexagon/translate.c | 4 +-- > target/riscv/common-semi-target.c | 37 ++++++++++++------- > target/riscv/cpu.c | 4 +++ > target/riscv/cpu.h | 2 +- > target/riscv/internals.h | 2 ++ > 24 files changed, 161 insertions(+), 80 deletions(-) >
This was merged into master (2cab0c10632960c01972727608196984d52c93bf). Regards, Pierrick
