From: Jonathan Cameron <[email protected]> Add the mpam-msc-cache subtype for cache components, with the cache-level/cache-type/cpu properties the board uses to place the MSC in the cache topology. Its realize assembles the cache identity view of MPAMF_IDR (same as the memory side, plus SP4=0 for RME) and IIDR/AIDR; the CPOR/CCAP/PRI feature bits arrive with their respective partitioning patches.
Based on an RFC series by Jonathan Cameron. Signed-off-by: Jonathan Cameron <[email protected]> Signed-off-by: Jinjie Ruan <[email protected]> --- hw/arm/mpam.c | 87 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/hw/arm/mpam.c b/hw/arm/mpam.c index 8a85c3b..17ca286 100644 --- a/hw/arm/mpam.c +++ b/hw/arm/mpam.c @@ -264,11 +264,22 @@ typedef struct MPAMMSCMemState { MPAMMSCState parent; } MPAMMSCMemState; +typedef struct MPAMMSCCacheState { + MPAMMSCState parent; + uint8_t cache_level; + uint8_t cache_type; + uint16_t cpu; + +} MPAMMSCCacheState; + DECLARE_INSTANCE_CHECKER(MPAMMSCState, MPAM_MSC_DEVICE, TYPE_MPAM_MSC); DECLARE_INSTANCE_CHECKER(MPAMMSCMemState, MPAM_MSC_MEM_DEVICE, TYPE_MPAM_MSC_MEM); +DECLARE_INSTANCE_CHECKER(MPAMMSCCacheState, MPAM_MSC_CACHE_DEVICE, + TYPE_MPAM_MSC_CACHE); + static uint64_t mpam_msc_read_reg(void *opaque, hwaddr offset, unsigned size) { @@ -420,12 +431,72 @@ static void mpam_msc_mem_realize(DeviceState *dev, Error **errp) } } +static void mpam_msc_cache_realize(DeviceState *dev, Error **errp) +{ + MPAMMSCState *s = MPAM_MSC_DEVICE(dev); + int i; + + mpam_msc_realize(dev, errp); + + for (i = 0; i < s->num_ris; i++) { + Mpamf *mpamf = &s->mpamf[i]; + + mpamf->idr = FIELD_DP64(mpamf->idr, MPAMF_IDR, PART_ID_MAX, + s->num_partid - 1); + /* No PCMG for now */ + mpamf->idr = FIELD_DP64(mpamf->idr, MPAMF_IDR, PMG_MAX, 0); + mpamf->idr = FIELD_DP64(mpamf->idr, MPAMF_IDR, EXT, 1); + mpamf->idr = FIELD_DP64(mpamf->idr, MPAMF_IDR, HAS_RIS, s->num_ris > 1); + mpamf->idr = FIELD_DP64(mpamf->idr, MPAMF_IDR, RIS_MAX, + s->num_ris > 1 ? s->num_ris - 1 : 0); + + /* Optional - test with and without */ + mpamf->idr = FIELD_DP64(mpamf->idr, MPAMF_IDR, HAS_ESR, 1); + mpamf->idr = FIELD_DP64(mpamf->idr, MPAMF_IDR, HAS_EXTD_ESR, + s->num_ris > 1); + + /* We won't implement any implementation specific stuff */ + mpamf->idr = FIELD_DP64(mpamf->idr, MPAMF_IDR, NO_IMPL_PART, 1); + mpamf->idr = FIELD_DP64(mpamf->idr, MPAMF_IDR, NO_IMPL_MSMON, 1); + + /* Need to implement for RME */ + mpamf->idr = FIELD_DP64(mpamf->idr, MPAMF_IDR, SP4, 0); + + mpamf->idr = FIELD_DP64(mpamf->idr, MPAMF_IDR, HAS_PARTID_NRW, + s->num_int_partid < s->num_partid); + + mpamf->iidr = FIELD_DP32(mpamf->iidr, MPAMF_IIDR, IMPLEMENTER, + MPAM_IIDR_IMPLEMENTER); + mpamf->iidr = FIELD_DP32(mpamf->iidr, MPAMF_IIDR, REVISION, 0); + mpamf->iidr = FIELD_DP32(mpamf->iidr, MPAMF_IIDR, VARIANT, 0); + /* FIXME get allocation for this emulation */ + mpamf->iidr = FIELD_DP32(mpamf->iidr, MPAMF_IIDR, PRODUCT_ID, 42); + + mpamf->aidr = FIELD_DP32(mpamf->aidr, MPAMF_AIDR, ARCH_MINOR_REV, 1); + mpamf->aidr = FIELD_DP32(mpamf->aidr, MPAMF_AIDR, ARCH_MAJOR_REV, 1); + + if (s->num_int_partid < s->num_partid) { + mpamf->partid_nrw_idr = FIELD_DP32(mpamf->partid_nrw_idr, + MPAMF_PARTID_NRW_IDR, + INTPARTID_MAX, + s->num_int_partid - 1); + } + /* TODO: Initialize all on as if firmware had done it for us */ + } +} + static const Property mpam_msc_props[] = { DEFINE_PROP_UINT8("num-ris", MPAMMSCState, num_ris, 1), DEFINE_PROP_UINT32("num-partid", MPAMMSCState, num_partid, 1), DEFINE_PROP_UINT32("num-int-partid", MPAMMSCState, num_int_partid, 0), }; +static const Property mpam_msc_cache_props[] = { + DEFINE_PROP_UINT8("cache-level", MPAMMSCCacheState, cache_level, 1), + DEFINE_PROP_UINT8("cache-type", MPAMMSCCacheState, cache_type, 1), + DEFINE_PROP_UINT16("cpu", MPAMMSCCacheState, cpu, 2), +}; + static void mpam_msc_init(ObjectClass *klass, const void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -440,6 +511,14 @@ static void mpam_msc_mem_init(ObjectClass *klass, const void *data) dc->realize = mpam_msc_mem_realize; } +static void mpam_msc_cache_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = mpam_msc_cache_realize; + device_class_set_props(dc, mpam_msc_cache_props); +} + static const TypeInfo mpam_msc_info = { .name = TYPE_MPAM_MSC, .parent = TYPE_SYS_BUS_DEVICE, @@ -454,9 +533,17 @@ static const TypeInfo mpam_msc_mem_info = { .class_init = mpam_msc_mem_init }; +static const TypeInfo mpam_msc_cache_info = { + .name = TYPE_MPAM_MSC_CACHE, + .parent = TYPE_MPAM_MSC, + .instance_size = sizeof(MPAMMSCCacheState), + .class_init = mpam_msc_cache_init +}; + static void mpam_register_types(void) { type_register_static(&mpam_msc_info); type_register_static(&mpam_msc_mem_info); + type_register_static(&mpam_msc_cache_info); } type_init(mpam_register_types); -- 2.43.0
