On Thu, 15 Oct 2026 at 19:11, Marcelo Manzo <[email protected]> wrote:
>
> Add the PCI-facing "root" part (D0:F0) of the BCM2838 (Raspberry Pi
> 4B / BCM2711) PCIe Root Complex: a PCIe root port with the vendor's
> device/vendor IDs and capability offsets, not usable on its own
> without the host-facing part added in the next patch.
>
> Adapted from patch 13/41 of Sergey Kambalin's "Raspberry Pi 4B
> machine" series (patchwork series 829638, posted to qemu-devel in
> 2024 but never merged) against current QEMU master; the surrounding
> PCIe/GENET networking support for raspi4b was left unmerged upstream
> (base scaffolding aside), so this and the following patches complete
> and debug that series to get real networking working under
> raspi4b.
>
> Signed-off-by: Marcelo Manzo <[email protected]>
> ---
> hw/arm/bcm2838_pcie.c | 82 +++++++++++++++++++++++++++++++++++
> hw/arm/meson.build | 4 +-
> include/hw/arm/bcm2838_pcie.h | 53 ++++++++++++++++++++++
> 3 files changed, 138 insertions(+), 1 deletion(-)
> create mode 100644 hw/arm/bcm2838_pcie.c
> create mode 100644 include/hw/arm/bcm2838_pcie.h
> +static void bcm2838_pcie_root_class_init(ObjectClass *class, const void
> *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(class);
> + PCIDeviceClass *k = PCI_DEVICE_CLASS(class);
> + ResettableClass *rc = RESETTABLE_CLASS(class);
> + PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(class);
> +
> + dc->desc = "BCM2711 PCIe Bridge";
> + /*
> + * PCI-facing part of the host bridge, not usable without the host-facing
> + * part, which can't be device_add'ed.
> + */
This comment is supposed to be next to the line that
sets dc->user_creatable = false, because it is the rationale
for why we do that, but it's got separated from it.
> +
> + resettable_class_set_parent_phases(rc, NULL,
> + bcm2838_pcie_root_port_reset_hold,
> + NULL, &rpc->parent_phases);
> +
> + dc->user_creatable = false;
> + k->vendor_id = BCM2838_PCIE_VENDOR_ID;
> + k->device_id = BCM2838_PCIE_DEVICE_ID;
> + k->revision = BCM2838_PCIE_REVISION;
> +
> + rpc->exp_offset = BCM2838_PCIE_EXP_CAP_OFFSET;
> + rpc->aer_offset = BCM2838_PCIE_AER_CAP_OFFSET;
> +}
> +struct BCM2838PcieRootState {
> + /*< private >*/
> + PCIESlot parent_obj;
> +
> + /*< public >*/
> + uint8_t regs[BCM2838_PCIE_REGS_SIZE - PCIE_CONFIG_SPACE_SIZE];
> +};
If this is register state doesn't it need to be in a vmstate
struct, or does it get migrated some other way by the PCI core code ?
thanks
-- PMM
