On Thu, 15 Oct 2026 at 19:11, Marcelo Manzo <[email protected]> wrote: > > Wire the BCM2838 PCIe host bridge into the SoC's peripheral block: > instantiate it, map its RC registers and MMIO window. > > Per Peter Maydell's review of a later follow-up series, fold in the > remaining defect from what was originally a separate bugfix here, > since this device isn't in upstream git yet: the PCI MMIO window was > mapped at the ARM base address with no address translation, even > though PCIE_MMIO_OFFSET was defined for exactly that purpose (and > otherwise unused). The DTB declares CPU 0x600000000 as mapping to PCI > 0xc0000000, so a guest would read PCI address 0 where it expected a > device BAR. Map an alias at the correct PCI offset instead. > > Signed-off-by: Marcelo Manzo <[email protected]> > ---
Reviewed-by: Peter Maydell <[email protected]> thanks -- PMM
