Factor sh4_exception_name() out of superh_cpu_do_interrupt() and register it as the CPUClass::exception_name() handler, so the common exception logging can resolve SH-4 exception codes to names.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Reviewed-by: Pierrick Bouvier <[email protected]> --- target/sh4/cpu.h | 1 + target/sh4/cpu.c | 1 + target/sh4/helper.c | 101 +++++++++++++++++++++++--------------------- 3 files changed, 56 insertions(+), 47 deletions(-) diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index a1e9049b7be..94f2f1278b9 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -258,6 +258,7 @@ struct SuperHCPUClass { uint32_t cvr; }; +const char *sh4_exception_name(int excp); void superh_cpu_dump_state(CPUState *cpu, FILE *f, int flags); int superh_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int superh_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 3bbdee301d5..97a718c3911 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -334,6 +334,7 @@ static void superh_cpu_class_init(ObjectClass *oc, const void *data) &scc->parent_phases); cc->class_by_name = superh_cpu_class_by_name; + cc->exception_name = sh4_exception_name; cc->dump_state = superh_cpu_dump_state; cc->set_pc = superh_cpu_set_pc; cc->get_pc = superh_cpu_get_pc; diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 0fbd613f333..5856bab6983 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -47,6 +47,58 @@ #define MMU_DADDR_ERROR_READ (-12) #define MMU_DADDR_ERROR_WRITE (-13) +const char *sh4_exception_name(int excp) +{ + const char *name; + + switch (excp) { + case SH4_EXCP_ADDR_ERROR: + name = "addr_error"; + break; + case SH4_EXCP_TLB_MISS: + name = "tlb_miss"; + break; + case SH4_EXCP_TLB_VIOLATION: + name = "tlb_violation"; + break; + case SH4_EXCP_ILLEGAL_INSTRUCTION: + name = "illegal_instruction"; + break; + case SH4_EXCP_SLOT_ILLEGAL_INSTRUCTION: + name = "slot_illegal_instruction"; + break; + case SH4_EXCP_FPU_DISABLE: + name = "fpu_disable"; + break; + case SH4_EXCP_SLOT_FPU_DISABLE: + name = "slot_fpu"; + break; + case SH4_EXCP_DATA_WRITE: + name = "data_write"; + break; + case SH4_EXCP_DTLB_MISS_WRITE: + name = "dtlb_miss_write"; + break; + case SH4_EXCP_DTLB_VIOLATION_WRITE: + name = "dtlb_violation_write"; + break; + case SH4_EXCP_FPU: + name = "fpu_exception"; + break; + case SH4_EXCP_INITIAL_PAGE_WRITE: + name = "initial_page_write"; + break; + case SH4_EXCP_TRAPA: + name = "trapa"; + break; + default: + name = "???"; + break; + } + + return name; +} + #if defined(CONFIG_USER_ONLY) int cpu_sh4_is_cached(CPUSH4State *env, uint32_t addr) @@ -95,53 +147,8 @@ void superh_cpu_do_interrupt(CPUState *cs) } if (qemu_loglevel_mask(CPU_LOG_INT)) { - const char *expname; - switch (cs->exception_index) { - case SH4_EXCP_ADDR_ERROR: - expname = "addr_error"; - break; - case SH4_EXCP_TLB_MISS: - expname = "tlb_miss"; - break; - case SH4_EXCP_TLB_VIOLATION: - expname = "tlb_violation"; - break; - case SH4_EXCP_ILLEGAL_INSTRUCTION: - expname = "illegal_instruction"; - break; - case SH4_EXCP_SLOT_ILLEGAL_INSTRUCTION: - expname = "slot_illegal_instruction"; - break; - case SH4_EXCP_FPU_DISABLE: - expname = "fpu_disable"; - break; - case SH4_EXCP_SLOT_FPU_DISABLE: - expname = "slot_fpu"; - break; - case SH4_EXCP_DATA_WRITE: - expname = "data_write"; - break; - case SH4_EXCP_DTLB_MISS_WRITE: - expname = "dtlb_miss_write"; - break; - case SH4_EXCP_DTLB_VIOLATION_WRITE: - expname = "dtlb_violation_write"; - break; - case SH4_EXCP_FPU: - expname = "fpu_exception"; - break; - case SH4_EXCP_INITIAL_PAGE_WRITE: - expname = "initial_page_write"; - break; - case SH4_EXCP_TRAPA: - expname = "trapa"; - break; - default: - expname = do_irq ? "interrupt" : "???"; - break; - } - qemu_log("exception 0x%03x [%s] raised\n", - irq_vector, expname); + qemu_log("exception 0x%03x [%s] raised\n", irq_vector, + do_irq ? "interrupt" : sh4_exception_name(cs->exception_index)); log_cpu_state(cs, 0); } -- 2.55.0
