On Wed, Oct 14, 2026 at 9:23 AM Bin Meng <[email protected]> wrote: > > The microchip-icicle-kit machine was originally validated with an older > Hart Software Services (HSS) firmware stack. HSS v2026.04.1 cannot boot > through U-Boot to Linux because several firmware-visible parts of the > PolarFire SoC are missing or incomplete. > > The first failure occurs before the UART is initialized because the L2 > zero window is not mapped. HSS then needs additional L2 cache controller > and DDR training behavior. Later boot stages exercise system services, > the RTC, SDHC version 4 DMA, and high-capacity SD card block sizing, > along with the complete DDR aliases. The existing models ither reject > these accesses or expose behavior that does not match the hardware > specifications. > > This series restores the complete firmware boot flow. With these > changes, QEMU boots the HSS v2026.04.1 eNVM image, loads its U-Boot > payload from an SD card, and reaches the Buildroot 2026.05 Linux > login prompt. > > The changes are organized around the firmware boot sequence: > > * Correct the L2-LIM size, map the L2 zero window, and provide the DMC > status transitions required by HSS DDR initialization. > * Model the documented L2CC Config, WayEnable, and WayMask registers, > and resize L2-LIM as cache ways are enabled. > * Complete SDHCI version 4 support used by the Cadence controller, > including Host Control 2, SDMA system addressing, 64-bit ADMA2 > descriptors, and SDMA boundary continuation. > * Run ADMA from a bounded timer-driven engine instead of performing work > from command or unrelated MMIO accesses. This keeps DMA progress > independent of guest register traffic and avoids consuming a polling > deadline inside the command write. > * Keep SDHC and SDXC memory transfers at their fixed 512-byte block > size, and advertise the Cadence controller's 64-bit system bus > support. > * Add the PolarFire SoC serial-number system service and RTC, and honor > the system-service notification control bit. > * Correct the DDR aliases and fix the board topology at its physical > configuration of 2 GiB of RAM and five harts. > * Document direct and HSS boot, add focused qtests and a full firmware > functional test, and restore the machine's Supported maintainer > status. > > Testing performed: > > * Built qemu-system-riscv64 and the documentation. > * Passed various newly added qtests. > * Booted HSS v2026.04.1, U-Boot, and Buildroot 2026.05 Linux to > the login prompt using the functional-test image. > > The functional test uses the processmission/qemu-machine-images release > v1.1.1 tarball: > > https://github.com/processmission/qemu-machine-images/releases/download/ > v1.1.1/riscv64-microchip-icicle-kit-v1.1.1.tar.zst > > When restoring the HSS boot support, 3 potential bugs were identified in > the upstream HSS source codes that either blocks the DDR training from > succeed or traps in a multi-core race at the very beginning or after > a succesfully DDR training but stuck at OpenSBI/U-Boot hand-off. There > are already bug reports filed aginst various upstream projects. > > Changes in v4: > - Drop the unused ADMA callback forward declaration > - Move helper definitions before the data-transfer declaration > - Merge the ADMA timer callback and batch routine > - Use HSS v2026.04.1 and the v1.1.1 test-image recipe > - Select the SoftConsole toolchain explicitly > - Use the generated complete boot-mode-1 eNVM binary > - Use the v1.1.1 test images with HSS v2026.04.1 > - Add the execution bit to the python script > - Collect Conor Dooley's Tested-by for the complete series > - Collect Bernhard Beschow's Tested-by for the ADMA patch >
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