On Mon, Oct 19, 2026 at 12:26 PM Brian Cain <[email protected]> wrote: > > Add decode and translation for trap2 and the vallocframe and vdeallocframe > instruction forms introduced with v83. Model vector stack overflow as a > precise exception and report it to linux-user as SIGSEGV. > > Teach the IDEF parser about VSP and vector frame checks. Describe the > vallocframe and vdeallocframe instruction semantics in system.idef, and move > the vector stack overflow check into a shared TCG generator helper. > > Reviewed-by: Pierrick Bouvier <[email protected]> > > Reviewed-by: Pierrick Bouvier <[email protected]> > Signed-off-by: Brian Cain <[email protected]> > --- > target/hexagon/cpu_bits.h | 1 + > target/hexagon/gen_tcg.h | 51 +++++++++++++++++++++ > target/hexagon/genptr.h | 1 + > target/hexagon/hex_regs.h | 2 + > target/hexagon/idef-parser/parser-helpers.h | 1 + > target/hexagon/translate.h | 1 + > linux-user/hexagon/cpu_loop.c | 4 ++ > target/hexagon/cpu.c | 2 +- > target/hexagon/genptr.c | 21 +++++++++ > target/hexagon/hexswi.c | 5 ++ > target/hexagon/idef-parser/parser-helpers.c | 14 ++++++ > target/hexagon/translate.c | 2 +- > target/hexagon/tag_rev_info.c.inc | 10 ++++ > target/hexagon/gen_idef_parser_funcs.py | 2 +- > target/hexagon/idef-parser/idef-parser.lex | 8 ++++ > target/hexagon/idef-parser/idef-parser.y | 9 +++- > target/hexagon/imported/encode_pp.def | 5 ++ > target/hexagon/imported/system.idef | 8 ++++ > 18 files changed, 143 insertions(+), 4 deletions(-) >
trap2 goes to the wrong vector. It should send event 10, but sends event 9, because it's hooked up to trap1. There is no HEX_EVENT_TRAP2 yet. register_trap_exception, hexagon_cpu_do_interrupt and event_name need some trap2 specific code. find_iclass_slots and decode_opcode_can_jump also need trap2. trap1 is also missing but maybe that should go in another patch.
