On 9/14/26 18:00, Peter Maydell wrote:
The IRS_IST_BASER.ADDR documentation says:For IRS_IST_CFGR.STRUCTURE = 0: Bits[N:0] of the resulting address are 0 where N depends on the ISTSZ and LPI_ID_BITS fields in IRS_IST_CFGR as follows: N = Max(5, (ISTSZ + 1) + LPI_ID_BITS) For IRS_IST_CFGR.STRUCTURE = 1: Bits[N:0] of the resulting address are 0 where N depends on L2SZ, ISTSZ, and LPI_ID_BITS in IRS_IST_CFGR as follows: N = Max(5, LPI_ID_BITS - ((10 - ISTSZ) + (2 * L2SZ)) + 2) This enforces that the IST is aligned to the size of the IST table, or to a 64-byte boundary if the table is smaller than 64 bytes, even if the guest programs the low bits in the ADDR field to specify an insufficiently aligned address. We were missing this check, and instead trusted the guest-provided address to be sufficiently aligned already; add the alignment enforcement. The GICv5 spec defines the masking to be used with the expressions quoted above, which work with the raw field values from the IRS_IST_CFGR register; these simplify down to some straightforward expressions based on the sanitized values we've already extracted form those fields. You can get to the expressions we use here either by working through the simplification of the GIC spec expressions, or from first principles (the number of bits needed for the size of the table in bytes is the number of bits that index it plus the number of bits specifying the size of an individual table entry). Signed-off-by: Peter Maydell<[email protected]> --- hw/intc/arm_gicv5.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+)
Reviewed-by: Richard Henderson <[email protected]> r~
