On 10/21/2026 8:08 AM, Ralf Ramsauer wrote:
From: Ralf Ramsauer <[email protected]> Whether a hart has supervisor mode is decided in two places: KVM harts always have it, and for TCG it follows from RVS in the ISA string. riscv_plic_hart_config_string() already spells out both cases. Board code needs the same answer to describe the interrupt controller, but it should not have to reach into CPURISCVState for it. Add a helper next to riscv_cpu_is_vendor() so the next patches can ask the CPU instead of inspecting its internals. Suggested-by: Daniel Henrique Barboza <[email protected]> Signed-off-by: Ralf Ramsauer <[email protected]> ---
Reviewed-by: Daniel Henrique Barboza <[email protected]>
target/riscv/cpu.c | 14 ++++++++++++++ target/riscv/cpu.h | 1 + 2 files changed, 15 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index da4c1a090b..19b6553e04 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -334,6 +334,20 @@ bool riscv_cpu_is_vendor(Object *cpu_obj) return object_dynamic_cast(cpu_obj, TYPE_RISCV_VENDOR_CPU) != NULL; }+bool riscv_cpu_has_supervisor_mode(RISCVCPU *cpu)+{ +#ifndef CONFIG_USER_ONLY + /* KVM always provides supervisor mode, regardless of the ISA string */ + if (kvm_enabled()) { + return true; + } + + return riscv_has_ext(&cpu->env, RVS); +#else + return false; +#endif +} + const char * const riscv_int_regnames[] = { "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8c8ffe94cd..535e56345f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -964,6 +964,7 @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext); bool riscv_cpu_is_vendor(Object *cpu_obj); +bool riscv_cpu_has_supervisor_mode(RISCVCPU *cpu);typedef struct isa_ext_data {const char *name;
