FLEXCAN_CRC_MBCRC is defined as (((x) & FLEXCAN_CRCR_MBCRC_MASK) << 16) but FLEXCAN_CRCRC_MBCRC_MASK is (like the other _MASK values in this header) defined to be an in-place mask FLEXCAN_GENMASK(22, 16) (a value with bits set from 16 to 22). The mask and shift operations are done in the wrong order, and so the result of the macro can only ever be zero.
Fix the macro to shift first and mask second. Cc: [email protected] Fixes: 3c4e23cbb597 ("hw/net/can/flexcan: NXP FlexCAN core emulation") Resolves: Coverity CID 1662973 Signed-off-by: Peter Maydell <[email protected]> --- hw/net/can/flexcan_regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/net/can/flexcan_regs.h b/hw/net/can/flexcan_regs.h index c18bc4736e5..7923bf836ff 100644 --- a/hw/net/can/flexcan_regs.h +++ b/hw/net/can/flexcan_regs.h @@ -150,7 +150,7 @@ /* FLEXCAN CRC Register (CRCR) bits */ #define FLEXCAN_CRCR_MBCRC_MASK FLEXCAN_GENMASK(22, 16) -#define FLEXCAN_CRCR_MBCRC(x) (((x) & FLEXCAN_CRCR_MBCRC_MASK) << 16) +#define FLEXCAN_CRCR_MBCRC(x) (((x) << 16) & FLEXCAN_CRCR_MBCRC_MASK) #define FLEXCAN_CRCR_TXCRC_MASK FLEXCAN_GENMASK(14, 0) #define FLEXCAN_CRCR_TXCRC(x) ((x) & FLEXCAN_CRCR_TXCRC_MASK) -- 2.43.0
