On Thu, Oct 22, 2026 at 11:51:03PM +0800, Philippe Mathieu-Daudé wrote:
> Factor riscv_excp_name() and riscv_intr_name() out of
> riscv_cpu_get_trap_name(). Register riscv_excp_name()
> as the CPUClass::exception_name() handler, so the common
> exception logging can resolve RISCV exception codes to names.
>
> Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
> Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Chao Liu <[email protected]>
Thanks,
Chao
> ---
> target/riscv/cpu.h | 1 +
> target/riscv/cpu.c | 20 ++++++++++----------
> target/riscv/tcg/op_helper.c | 2 +-
> 3 files changed, 12 insertions(+), 11 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index b65d6319940..49a1186bdbb 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -672,6 +672,7 @@ G_NORETURN void riscv_cpu_do_unaligned_access(CPUState
> *cs, vaddr addr,
> bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> MMUAccessType access_type, int mmu_idx,
> bool probe, uintptr_t retaddr);
> +const char *riscv_excp_name(int excp);
> char *riscv_isa_string(RISCVCPU *cpu);
> int riscv_cpu_max_xlen(RISCVCPUClass *mcc);
> bool riscv_cpu_option_set(RISCVCPU *cpu, const char *optname);
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 08a4d14ea1f..e1652bd2a40 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -18,6 +18,7 @@
> */
>
> #include "qemu/osdep.h"
> +#include "qemu/cutils.h"
> #include "qemu/qemu-print.h"
> #include "qemu/ctype.h"
> #include "qemu/log.h"
> @@ -398,6 +399,11 @@ static const char * const riscv_excp_names[] = {
> [RISCV_EXCP_SEMIHOST] = "semihost",
> };
>
> +const char *riscv_excp_name(int excp)
> +{
> + return STR_ARRAY_ELEM_OR_NULL(riscv_excp_names, excp) ?: "unknown";
> +}
> +
> static const char * const riscv_intr_names[] = {
> [IRQ_U_SOFT] = "u_software",
> [IRQ_S_SOFT] = "s_software",
> @@ -417,17 +423,10 @@ static const char * const riscv_intr_names[] = {
>
> const char *riscv_cpu_get_trap_name(uint64_t cause, bool async)
> {
> - if (async) {
> - if ((cause < ARRAY_SIZE(riscv_intr_names)) &&
> riscv_intr_names[cause]) {
> - return riscv_intr_names[cause];
> - }
> - } else {
> - if ((cause < ARRAY_SIZE(riscv_excp_names)) &&
> riscv_excp_names[cause]) {
> - return riscv_excp_names[cause];
> - }
> - }
> + const char *name = async ? STR_ARRAY_ELEM_OR_NULL(riscv_intr_names,
> cause)
> + : STR_ARRAY_ELEM_OR_NULL(riscv_excp_names,
> cause);
>
> - return "(unknown)";
> + return name ?: "unknown";
> }
>
> void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext)
> @@ -3128,6 +3127,7 @@ static void riscv_cpu_common_class_init(ObjectClass *c,
> const void *data)
> &mcc->parent_phases);
>
> cc->class_by_name = riscv_cpu_class_by_name;
> + cc->exception_name = riscv_excp_name;
> cc->dump_state = riscv_cpu_dump_state;
> cc->set_pc = riscv_cpu_set_pc;
> cc->get_pc = riscv_cpu_get_pc;
> diff --git a/target/riscv/tcg/op_helper.c b/target/riscv/tcg/op_helper.c
> index b8b3e43ccd5..f85f5cd83c9 100644
> --- a/target/riscv/tcg/op_helper.c
> +++ b/target/riscv/tcg/op_helper.c
> @@ -41,7 +41,7 @@ G_NORETURN void riscv_raise_exception(CPURISCVState *env,
> CPUState *cs = env_cpu(env);
>
> trace_riscv_exception(exception,
> - riscv_cpu_get_trap_name(exception, false),
> + riscv_excp_name(exception),
> env->pc);
>
> cs->exception_index = exception;
> --
> 2.55.0
>
