Hi Timur,
On 26/10/26 22:28, Timur Maksimov wrote:
The BUSY status is moved to I2CC_MS_TXRX_BYTE_BUF register instead of I2CM_CMD
in new register mode.
Slighly clearer:
'''
In new register mode, BUS_BUSY_STS is bit 16 of I2CC_MS_TXRX_BYTE_BUF;
bit 16 of I2CM_CMD is PKT_OP_EN. Report the bus busy state in the
correct register.
'''
Fixes: ba2cccd64e90 ("aspeed: i2c: Add new mode support")
Signed-off-by: Timur Maksimov [email protected]
Email goes withing angle brackets (same applies to other patches):
Signed-off-by: Timur Maksimov <[email protected]>
---
hw/i2c/aspeed_i2c.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
index 376e113e58..a2b4c8b576 100644
--- a/hw/i2c/aspeed_i2c.c
+++ b/hw/i2c/aspeed_i2c.c
@@ -147,7 +147,7 @@ static uint64_t aspeed_i2c_bus_new_read(AspeedI2CBus *bus,
hwaddr offset,
case A_I2CC_POOL_CTRL:
case A_I2CM_INTR_CTRL:
case A_I2CM_INTR_STS:
- case A_I2CC_MS_TXRX_BYTE_BUF:
+ case A_I2CM_CMD:
case A_I2CM_DMA_LEN:
case A_I2CM_DMA_TX_ADDR:
case A_I2CM_DMA_RX_ADDR:
@@ -167,7 +167,7 @@ static uint64_t aspeed_i2c_bus_new_read(AspeedI2CBus *bus,
hwaddr offset,
case A_I2CC_DMA_ADDR:
value = extract64(bus->dma_dram_offset, 0, 32);
break;
- case A_I2CM_CMD:
+ case A_I2CC_MS_TXRX_BYTE_BUF:
value = bus->regs[offset / sizeof(*bus->regs)];
This patch should be re-ordered before the #2 one IIUC,
otherwise the fix is correct:
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
value = SHARED_FIELD_DP32(value, BUS_BUSY_STS,
i2c_bus_busy(bus->bus));
break;
Thanks,
Phil.
