MMU_USER_IDX is defined as 3, but the RISC-V user-mode MMU index
is MMUIdx_U, which is 0. This macro is used by the generic
cpu_mmu_index() for CONFIG_USER_ONLY builds and must match
riscv_env_mmu_index(), so fix the value to 0.
Fixes: dc5bd18fa572 ("RISC-V CPU Core Definition")
Signed-off-by: Wang Yechao <[email protected]>
---
Changes in v3:
- Keep the MMU_USER_IDX macro because cpu_mmu_index() needs it.
- Link to v2:
https://lore.kernel.org/qemu-devel/[email protected]/
Changes in v2:
- Adjust the patch descriptions and rebased on riscv-to-apply.next.
- Link to v1:
https://lore.kernel.org/qemu-devel/[email protected]/
target/riscv/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index b65d631994..aaf16231de 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -180,7 +180,7 @@ extern RISCVCPUImpliedExtsRule
*riscv_multi_ext_implied_rules[];
#define RISCV_IMPLIED_EXTS_RULE_END -1
-#define MMU_USER_IDX 3
+#define MMU_USER_IDX 0 /* MMUIdx_U */
#if !defined(CONFIG_USER_ONLY)
#include "tcg/pmp.h"
--
2.27.0
