Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Brian Cain <[email protected]>
---
hw/hexagon/machine_cfg_sa8797p_nsp0.h.inc | 56 +++++++++++++++++++
hw/hexagon/sa8797p_nsp0.c | 68 +++++++++++++++++++++++
tests/qtest/l2vic-test.c | 2 +
tests/qtest/qcom-dsp-test.c | 1 +
tests/qtest/qct-qtimer-test.c | 2 +
hw/hexagon/Kconfig | 6 ++
hw/hexagon/meson.build | 1 +
7 files changed, 136 insertions(+)
create mode 100644 hw/hexagon/machine_cfg_sa8797p_nsp0.h.inc
create mode 100644 hw/hexagon/sa8797p_nsp0.c
diff --git a/hw/hexagon/machine_cfg_sa8797p_nsp0.h.inc
b/hw/hexagon/machine_cfg_sa8797p_nsp0.h.inc
new file mode 100644
index 00000000000..abc02a3e9ce
--- /dev/null
+++ b/hw/hexagon/machine_cfg_sa8797p_nsp0.h.inc
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+static const struct hexagon_machine_config sa8797p_nsp0 = {
+ .ddr_base = 0x80000000,
+ .cfgbase = 0x30180000,
+ .l2vic_base = 0x32390000,
+ .l2vic_size = 0x1000,
+ .l2tcm_size = 0x100000,
+ .csr_base = 0x323a0000,
+ .qtmr_region = 0x323a1000,
+ .cfgtable = {
+ .l2tcm_base = 0x3000,
+ .subsystem_base = 0x3238,
+ .etm_base = 0x3019,
+ .l2cfg_base = 0x301a,
+ .l1s0_base = 0x3100,
+ .fastl2vic_base = 0x301e,
+ .jtlb_size_entries = 0x80,
+ .coproc_present = 0xd,
+ .ext_contexts = 8,
+ .vtcm_base = 0x3100,
+ .vtcm_size_kb = 0x4000,
+ .l2tag_size = 0x400,
+ .l2ecomem_size = 0x400,
+ .thread_enable_mask = 0xfff,
+ .eccreg_base = 0x301f,
+ .l2line_size = 0x80,
+ .l2itcm_base = 0x3000,
+ .dma_version = 8,
+ .hvx_vec_log_length = 7,
+ .coproc2_reg0 = 0x10,
+ .coproc2_reg1 = 8,
+ .v2x_mode = 1,
+ .acd_preset = 1,
+ .mnd_preset = 1,
+ .l1d_size_kb = 0x40,
+ .l1i_size_kb = 0x40,
+ .l1d_write_policy = 2,
+ .vtcm_bank_width = 0x80,
+ .reserved4 = 1,
+ .reserved6 = 3,
+ .consistency_domain = 0xe0,
+ .capacity_domain = 0x80,
+ .corecfg_present = 0xd,
+ .coproc2_fp16_acc_exp = 1,
+ .AXIM_data_width = 0x100,
+ .l1d_ways = 8,
+ .l1i_ways = 4,
+ .l2way_num = 8,
+ .dma_jtlb_entries = 0x40,
+ },
+};
diff --git a/hw/hexagon/sa8797p_nsp0.c b/hw/hexagon/sa8797p_nsp0.c
new file mode 100644
index 00000000000..20eebd5389f
--- /dev/null
+++ b/hw/hexagon/sa8797p_nsp0.c
@@ -0,0 +1,68 @@
+/*
+ * Models the v81 NSP0 of the SA8797P.
+ *
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "hw/core/boards.h"
+#include "hw/hexagon/hexagon.h"
+#include "hw/hexagon/qcom_dsp.h"
+#include "target/hexagon/cpu.h"
+
+#include "machine_cfg_sa8797p_nsp0.h.inc"
+
+#define TYPE_SA8797P_NSP0_MACHINE MACHINE_TYPE_NAME("sa8797p-nsp0")
+
+static const QcomDspRegion sa8797p_nsp0_regions[] = {
+ { "gcc", 0x00100000, 0x200000 },
+ { "ne-gcc", 0x08900000, 0x100000 },
+ { "se-gcc", 0x08a00000, 0x100000 },
+ { "nw-gcc", 0x08b00000, 0x100000 },
+ { "nsp-cc", 0x320c0000, 0x10000 },
+ { "qfprom", 0x360c8000, 0x8000 },
+ { "q6-cc", 0x32340000, 0x11000 },
+ { "pinctrl", 0x0f100000, 0x0f00000 },
+ { "ipcc", 0x09000000 },
+ { "ipcc-legacy", 0x32380000 },
+ { "stmtrace", 0x16000000, 0x1000000 },
+ { "tpdm", 0x117c0000, 0x2000 },
+ { "tpdm", 0x117c5000, 0x2000 },
+ { "tpda", 0x117c8000 },
+};
+
+static void sa8797p_nsp0_init_devices(MachineState *ms)
+{
+ qcom_dsp_add_regions(ms, sa8797p_nsp0_regions,
+ ARRAY_SIZE(sa8797p_nsp0_regions));
+
+ qcom_soc_add_qup_geni_ports("sa8797p", 0x09b86000, 5, 0x2000);
+ qcom_soc_add_qup_geni_ports("sa8797p", 0x09c06000, 5, 0x2000);
+ qcom_soc_add_qup_geni_ports("sa8797p", 0x00c80000, 1, 0x4000);
+ qcom_soc_add_qup_geni_ports("sa8797p", 0x00a80000, 7, 0x4000);
+ qcom_soc_add_qup_geni_ports("sa8797p", 0x00980000, 7, 0x4000);
+ qcom_soc_add_qup_geni_ports("sa8797p", 0x00880000, 7, 0x4000);
+ qcom_soc_add_qup_geni_ports("sa8797p", 0x198880000, 6, 0x4000);
+}
+
+static const QcomDspMachineInfo sa8797p_nsp0_info = {
+ .desc = "SA8797P NSP",
+ .cpu_type = HEXAGON_CPU_TYPE_NAME("v81"),
+ .cpus = 12,
+ .rev = v81_rev,
+ .cfg = &sa8797p_nsp0,
+ .kernel_addr = 0xa0000000,
+ .init_devices = sa8797p_nsp0_init_devices,
+};
+
+static const TypeInfo sa8797p_nsp0_types[] = {
+ {
+ .name = TYPE_SA8797P_NSP0_MACHINE,
+ .parent = TYPE_QCOM_DSP_MACHINE,
+ .class_init = qcom_dsp_class_init,
+ .class_data = &sa8797p_nsp0_info,
+ },
+};
+
+DEFINE_TYPES(sa8797p_nsp0_types)
diff --git a/tests/qtest/l2vic-test.c b/tests/qtest/l2vic-test.c
index 7afeabdbed8..4cd0319e8b5 100644
--- a/tests/qtest/l2vic-test.c
+++ b/tests/qtest/l2vic-test.c
@@ -12,6 +12,7 @@
#include "hw/hexagon/machine_cfg_v66g_1024.h.inc"
#include "hw/hexagon/machine_cfg_v68n_1024.h.inc"
#include "hw/hexagon/machine_cfg_qcs6490_cdsp.h.inc"
+#include "hw/hexagon/machine_cfg_sa8797p_nsp0.h.inc"
#include "hw/hexagon/machine_cfg_sc8480xp_nsp0.h.inc"
#include "hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc"
@@ -51,6 +52,7 @@ static const L2VICMachineCfg l2vic_machines[] = {
{ "qcs6490-cdsp", &qcs6490_cdsp },
{ "sa8775p-cdsp", &SA8775P_cdsp0 },
{ "sc8480xp-nsp0", &sc8480xp_nsp0 },
+ { "sa8797p-nsp0", &sa8797p_nsp0 },
};
static uint32_t l2vic_read32(uint64_t base, uint32_t offset)
diff --git a/tests/qtest/qcom-dsp-test.c b/tests/qtest/qcom-dsp-test.c
index 46bbae47881..def389a0e9e 100644
--- a/tests/qtest/qcom-dsp-test.c
+++ b/tests/qtest/qcom-dsp-test.c
@@ -26,6 +26,7 @@ static const char *const qcom_dsp_machines[] = {
"qcs6490-cdsp",
"sa8775p-cdsp",
"sc8480xp-nsp0",
+ "sa8797p-nsp0",
};
static void test_console(const void *machine)
diff --git a/tests/qtest/qct-qtimer-test.c b/tests/qtest/qct-qtimer-test.c
index 629a11802ef..21870de5649 100644
--- a/tests/qtest/qct-qtimer-test.c
+++ b/tests/qtest/qct-qtimer-test.c
@@ -13,6 +13,7 @@
#include "hw/hexagon/machine_cfg_v68n_1024.h.inc"
#include "hw/hexagon/machine_cfg_v66g_1024.h.inc"
#include "hw/hexagon/machine_cfg_qcs6490_cdsp.h.inc"
+#include "hw/hexagon/machine_cfg_sa8797p_nsp0.h.inc"
#include "hw/hexagon/machine_cfg_sc8480xp_nsp0.h.inc"
#include "hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc"
@@ -348,6 +349,7 @@ static const QtimerMachineCfg qtimer_machines[] = {
{ "qcs6490-cdsp", &qcs6490_cdsp },
{ "sa8775p-cdsp", &SA8775P_cdsp0 },
{ "sc8480xp-nsp0", &sc8480xp_nsp0 },
+ { "sa8797p-nsp0", &sa8797p_nsp0 },
};
static void test_qtimer_on_machine(gconstpointer data)
diff --git a/hw/hexagon/Kconfig b/hw/hexagon/Kconfig
index 8785129da0e..bcf368cb8b7 100644
--- a/hw/hexagon/Kconfig
+++ b/hw/hexagon/Kconfig
@@ -48,3 +48,9 @@ config HEX_SC8480XP_NSP0
default y
depends on HEX_DSP && FDT
select HEX_QCOM_DSP
+
+config HEX_SA8797P_NSP0
+ bool
+ default y
+ depends on HEX_DSP && FDT
+ select HEX_QCOM_DSP
diff --git a/hw/hexagon/meson.build b/hw/hexagon/meson.build
index b42a37b14de..5a10ae694fe 100644
--- a/hw/hexagon/meson.build
+++ b/hw/hexagon/meson.build
@@ -10,5 +10,6 @@ hexagon_ss.add(when: 'CONFIG_HEX_QCOM_DSP', if_true:
files('qcom_dsp.c'))
hexagon_ss.add(when: 'CONFIG_HEX_QCS6490_CDSP', if_true:
files('qcs6490_cdsp.c'))
hexagon_ss.add(when: 'CONFIG_HEX_SA8775P_CDSP', if_true:
files('sa8775p_cdsp.c'))
hexagon_ss.add(when: 'CONFIG_HEX_SC8480XP_NSP0', if_true:
files('sc8480xp_nsp0.c'))
+hexagon_ss.add(when: 'CONFIG_HEX_SA8797P_NSP0', if_true:
files('sa8797p_nsp0.c'))
hw_arch += {'hexagon': hexagon_ss}
--
2.34.1
