On 10/28/2026 11:25 AM, Philippe Mathieu-Daudé wrote: > MIPS has no XML target description, so extra features can not > be registered. Expose the cpu, cp0 and fpu registers as the GDB > standard features, mapped to the legacy register numbers. > > Registers are sized by the target long size (mips32-*.xml or > mips64-*.xml) instead of the CPU: a 32-bit CPU on a 64-bit target > now reports 64-bit registers. FPU registers are single-precision > on 32-bit targets. > > Signed-off-by: Philippe Mathieu-Daudé <[email protected]> > --- > MAINTAINERS | 1 + > configs/targets/mips-linux-user.mak | 1 + > configs/targets/mips-softmmu.mak | 1 + > configs/targets/mips64-linux-user.mak | 1 + > configs/targets/mips64-softmmu.mak | 1 + > configs/targets/mips64el-linux-user.mak | 1 + > configs/targets/mips64el-softmmu.mak | 1 + > configs/targets/mipsel-linux-user.mak | 1 + > configs/targets/mipsel-softmmu.mak | 1 + > configs/targets/mipsn32-linux-user.mak | 1 + > configs/targets/mipsn32el-linux-user.mak | 1 + > target/mips/internal.h | 2 + > target/mips/cpu.c | 4 ++ > target/mips/gdbstub.c | 86 ++++++++++++++++++++++++ > gdbstub/gdb-xml/mips32-cp0.xml | 9 +++ > gdbstub/gdb-xml/mips32-cpu.xml | 42 ++++++++++++ > gdbstub/gdb-xml/mips32-fpu.xml | 41 +++++++++++ > gdbstub/gdb-xml/mips64-cp0.xml | 9 +++ > gdbstub/gdb-xml/mips64-cpu.xml | 42 ++++++++++++ > gdbstub/gdb-xml/mips64-fpu.xml | 41 +++++++++++ > 20 files changed, 287 insertions(+) > create mode 100644 gdbstub/gdb-xml/mips32-cp0.xml > create mode 100644 gdbstub/gdb-xml/mips32-cpu.xml > create mode 100644 gdbstub/gdb-xml/mips32-fpu.xml > create mode 100644 gdbstub/gdb-xml/mips64-cp0.xml > create mode 100644 gdbstub/gdb-xml/mips64-cpu.xml > create mode 100644 gdbstub/gdb-xml/mips64-fpu.xml >
Reviewed-by: Pierrick Bouvier <[email protected]>
