This QEMU series adds support for the Sspesa (Precise Event Sample Attribution) extension.
The first patch adds the 'sspesa' and 'ssplcofi' CPU properties, the ISA string/DT entry, and the shpmspc/shpmsdata CSRs. It also adds dependency of Sspesa on Sscofpmf and of Ssplcofi on Sspesa. The second patch captures the overflowing counter ID, priv mode and pc for the first counter overflow. Note: QEMU does not currently identify any event as supporting precise attribution. The QEMU setup is intended to validate the end-to-end Sspesa plumbing only. Similarly, the `pesa=1` raw-event format bit in Linux is used to simulate an event that supports precise attribution. Such events are expected to be defined in vendor/platform specific JSON event files, but this series does not add such an event file for the 'Virt' machine. Reproducing the full setup: Sspesa support requires Linux, QEMU and OpenSBI. The matching v2 branches are: Linux: https://github.com/mdchitale/linux/tree/riscv_sspesa_rfc_v2 QEMU: https://github.com/mdchitale/qemu/tree/riscv_sspesa_rfc_v2 OpenSBI must be built with the following fix so that PMU overflow interrupts work correctly: https://lists.infradead.org/pipermail/opensbi/2026-October/010957.html Build Linux and QEMU from the branches above, and build OpenSBI with this fix applied. By default QEMU doesn't define a raw event that can be mapped to programmable counters and hence a special test DTB is required which includes the raw-event-to-counter mapping. Build the test DTB: - qemu-system-riscv64 -machine virt,dumpdtb=/tmp/virt-sspesa.dtb \ -cpu rv64,sspesa=true,ssplcofi=true,ssccfg=true,sscofpmf=true - dtc -I dtb -O dts -o /tmp/virt-sspesa.dts /tmp/virt-sspesa.dtb - Edit `/tmp/virt-sspesa.dts` and add the following property to the `/pmu` node: riscv,raw-event-to-mhpmcounters = <0x0 0x2 0x0 0xffffffffffff 0x7fff8>; - dtc -I dts -O dtb -o /tmp/virt-sspesa-test.dtb /tmp/virt-sspesa.dts Boot Linux with the test DTB: - qemu-system-riscv64 -nographic -machine virt \ -cpu rv64,sspesa=true,ssplcofi=true,ssccfg=true,sscofpmf=true \ -bios /path/to/fw_dynamic.bin -kernel /path/to/Image \ -drive file=/path/to/rootfs.img,id=hd0,format=raw,if=none \ -device virtio-blk-device,drive=hd0 \ -append "root=/dev/vda rw console=ttyS0 earlycon=sbi" \ -dtb /tmp/virt-sspesa-test.dtb Once Linux boots, use the PESA event modifier with a precise request: - perf record -o /tmp/sspesa-perf.data -e 'cpu/event=2,pesa=1/ppp' <workload> - perf record -o /tmp/non-sspesa-perf.data -e 'cpu/event=2/' <workload> Check the resulting data with: - perf report -D -i /tmp/sspesa-perf.data \ | grep 'PERF_RECORD_SAMPLE' | head - perf report -D -i /tmp/non-sspesa-perf.data \ | grep 'PERF_RECORD_SAMPLE' | head Samples in sspesa-perf.data should have the PERF_RECORD_MISC_EXACT_IP bit (0x4000) set in the misc field, while samples in non-sspesa-perf.data should not have that bit set. This verifies plumbing only regardless of whether QEMU supports precise attribution. Changes since v1: - Record the effective privilege mode in the new shpmsdata.PRIV field: https://github.com/riscv/riscv-performance-event-sampling/commit/3eff81a6161ffc7a74a57436132d0c15ab549e74 - Capture shpmspc at counter overflow, instead of during interrupt delivery. - Preserve the first sample as long as LCOFIP remains pending. - Update sample CSRs only for delegated counters when menvcfg.CDE=1. - Fix extension dependencies i.e. Sspesa implies Sscofpmf and Ssplcofi implies Sspesa. Mayuresh Chitale (2): target/riscv: Add Sspesa extension and sample CSRs target/riscv: Capture Sspesa sample PC and counter ID on overflow target/riscv/cpu.c | 24 ++++++++++++++ target/riscv/cpu.h | 4 +++ target/riscv/cpu_bits.h | 11 +++++++ target/riscv/cpu_cfg_fields.h.inc | 2 ++ target/riscv/machine.c | 20 +++++++++++ target/riscv/tcg/csr.c | 55 +++++++++++++++++++++++++++++++ target/riscv/tcg/pmu.c | 39 ++++++++++++++++++++++ 7 files changed, 155 insertions(+) -- 2.43.0
