In KVM mode, virt_get_caches() currently gets a zero value for the CLIDR_EL1 register. This is due to the fact CLIDR is never read from host. This is a bug.
Soon we will initialize all writable isar.idreg[] from host and this includes CLIDR_EL1. However, we cannot directly fix the initialization, first because it would change the way caches are exposed to guest in DT/ACPI descriptions and because some host values would be rejected by the current QEMU code, especially in the case host has a unified L1 cache which is currently not supported and triggers the following error: "Unified type is not implemented at level 1" error. So this issue will be fixed separately. Signed-off-by: Eric Auger <[email protected]> Reviewed-by: Khushit Shah <[email protected]> Reviewed-by: Gustavo Romero <[email protected]> --- v1 -> v2: - fix the commit msg and improved comment (Gustavo) --- hw/arm/virt.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 0d56197dac..a80c60f3fa 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -338,6 +338,21 @@ unsigned int virt_get_caches(const VirtMachineState *vms, CPUCoreCaches *caches) ARMISARegisters *isar = &armcpu->isar; uint32_t clidr = GET_IDREG(isar, CLIDR); + /* + * Commit f669de70011 ("hw/arm/virt: add cache hierarchy to device tree") + * read the CLIDR value from the isar array. However, in KVM mode, we failed + * to initialize that register value from host and the resulting bug is that + * we have always read 0. + * + * Soon we will initialize all writable isar.idreg[] from host, including + * CLIDR_EL1 but we will need to handle compat properly and also extend the + * support to unified L1 cache. For now do not pretend we have something + * different from 0. + */ + if (kvm_enabled()) { + clidr = 0; + } + for (int cache_level = 1; cache_level <= CLIDR_CTYPE_MAX_CACHE_LEVEL; cache_level++) { uint8_t ctype = -- 2.53.0
